From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
To: mjc@sifive.com, sagark@eecs.berkeley.edu, palmer@sifive.com,
kbastian@mail.uni-paderborn.de, Alistair.Francis@wdc.com
Cc: richard.henderson@linaro.org, peer.adelt@hni.uni-paderborn.de,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Subject: [Qemu-devel] [PATCH v3 33/35] target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
Date: Wed, 31 Oct 2018 14:20:27 +0100 [thread overview]
Message-ID: <20181031132029.4887-34-kbastian@mail.uni-paderborn.de> (raw)
In-Reply-To: <20181031132029.4887-1-kbastian@mail.uni-paderborn.de>
this finally removes the old decoder functions that we carried along
with it.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target/riscv/Makefile.objs | 1 +
target/riscv/insn16-32.decode | 24 ++++
target/riscv/insn16-64.decode | 4 +
target/riscv/insn16.decode | 7 +-
target/riscv/insn_trans/trans_rvc.inc.c | 22 ----
target/riscv/translate.c | 165 +-----------------------
6 files changed, 31 insertions(+), 192 deletions(-)
create mode 100644 target/riscv/insn16-32.decode
diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs
index 515c12b4f8..3086ef0c29 100644
--- a/target/riscv/Makefile.objs
+++ b/target/riscv/Makefile.objs
@@ -6,6 +6,7 @@ decode32-y = $(SRC_PATH)/target/riscv/insn32.decode
decode32-$(TARGET_RISCV64) += $(SRC_PATH)/target/riscv/insn64.decode
decode16-y = $(SRC_PATH)/target/riscv/insn16.decode
+decode16-$(TARGET_RISCV32) += $(SRC_PATH)/target/riscv/insn16-32.decode
decode16-$(TARGET_RISCV64) += $(SRC_PATH)/target/riscv/insn16-64.decode
target/riscv/decode_insn32.inc.c: $(decode32-y) $(DECODETREE)
diff --git a/target/riscv/insn16-32.decode b/target/riscv/insn16-32.decode
new file mode 100644
index 0000000000..e21a701056
--- /dev/null
+++ b/target/riscv/insn16-32.decode
@@ -0,0 +1,24 @@
+#
+# RISC-V translation routines for the RVC Instruction Set.
+#
+# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
+# Bastian Koppelmann, kbastian@mail.uni-paderborn.de
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2 or later, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+# more details.
+#
+# You should have received a copy of the GNU General Public License along with
+# this program. If not, see <http://www.gnu.org/licenses/>.
+
+# This is concatenated with insn16.decode for risc32 targets.
+# All of the fields and formats are there.
+
+# *** RV32C Standard Extension (Quadrant 0) ***
+flw 011 ... ... .. ... 00 @cl_w
+fsw 111 ... ... .. ... 00 @cs_w
diff --git a/target/riscv/insn16-64.decode b/target/riscv/insn16-64.decode
index 5af2e2b072..de97a45acf 100644
--- a/target/riscv/insn16-64.decode
+++ b/target/riscv/insn16-64.decode
@@ -19,6 +19,10 @@
# This is concatenated with insn16.decode for risc64 targets.
# All of the fields and formats are there.
+# *** RV64C Standard Extension (Quadrant 0) ***
+ld 011 ... ... .. ... 00 @cl_d
+sd 111 ... ... .. ... 00 @cs_d
+
# *** RV64C Standard Extension (Quadrant 1) ***
subw 100 1 11 ... 00 ... 01 @cs_2
addw 100 1 11 ... 01 ... 01 @cs_2
diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
index c215867ff9..b075336062 100644
--- a/target/riscv/insn16.decode
+++ b/target/riscv/insn16.decode
@@ -47,10 +47,9 @@
&s imm rs1 rs2 !extern
# Argument sets:
-&cl rs1 rd
&ci imm rd
&ciw nzuimm rd
-&cs rs1 rs2
+&cs_dw uimm rs1 rs2
&cb imm rs1
&cr rd rs2
&c_j imm
@@ -69,8 +68,6 @@
@ciw ... ........ ... .. &ciw nzuimm=%nzuimm_ciw rd=%rs2_3
@cl_d ... ... ... .. ... .. &i imm=%uimm_cl_d rs1=%rs1_3 rd=%rs2_3
@cl_w ... ... ... .. ... .. &i imm=%uimm_cl_w rs1=%rs1_3 rd=%rs2_3
-@cl ... ... ... .. ... .. &cl rs1=%rs1_3 rd=%rs2_3
-@cs ... ... ... .. ... .. &cs rs1=%rs1_3 rs2=%rs2_3
@cs_2 ... ... ... .. ... .. &r rd=%rs1_3 rs1=%rs1_3 rs2=%rs2_3
@cs_d ... ... ... .. ... .. &s imm=%uimm_cl_d rs1=%rs1_3 rs2=%rs2_3
@cs_w ... ... ... .. ... .. &s imm=%uimm_cl_w rs1=%rs1_3 rs2=%rs2_3
@@ -97,10 +94,8 @@
c_addi4spn 000 ........ ... 00 @ciw
fld 001 ... ... .. ... 00 @cl_d
lw 010 ... ... .. ... 00 @cl_w
-c_flw_ld 011 --- ... -- ... 00 @cl #Note: Must parse uimm manually
fsd 101 ... ... .. ... 00 @cs_d
sw 110 ... ... .. ... 00 @cs_w
-c_fsw_sd 111 --- ... -- ... 00 @cs #Note: Must parse uimm manually
# *** RV64C Standard Extension (Quadrant 1) ***
c_addi 000 . ..... ..... 01 @ci
diff --git a/target/riscv/insn_trans/trans_rvc.inc.c b/target/riscv/insn_trans/trans_rvc.inc.c
index d932bfd3e0..f521daf32e 100644
--- a/target/riscv/insn_trans/trans_rvc.inc.c
+++ b/target/riscv/insn_trans/trans_rvc.inc.c
@@ -28,28 +28,6 @@ static bool trans_c_addi4spn(DisasContext *ctx, arg_c_addi4spn *a)
return trans_addi(ctx, &arg);
}
-static bool trans_c_flw_ld(DisasContext *ctx, arg_c_flw_ld *a)
-{
-#ifdef TARGET_RISCV32
- /* C.FLW ( RV32FC-only ) */
- return false;
-#else
- /* C.LD ( RV64C/RV128C-only ) */
- return false;
-#endif
-}
-
-static bool trans_c_fsw_sd(DisasContext *ctx, arg_c_fsw_sd *a)
-{
-#ifdef TARGET_RISCV32
- /* C.FSW ( RV32FC-only ) */
- return false;
-#else
- /* C.SD ( RV64C/RV128C-only ) */
- return false;
-#endif
-}
-
static bool trans_c_addi(DisasContext *ctx, arg_c_addi *a)
{
if (a->imm == 0) {
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 56b650a9d7..1d4f848e9a 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -55,22 +55,6 @@ typedef struct DisasContext {
CPURISCVState *env;
} DisasContext;
-#ifdef TARGET_RISCV64
-/* convert riscv funct3 to qemu memop for load/store */
-static const int tcg_memop_lookup[8] = {
- [0 ... 7] = -1,
- [0] = MO_SB,
- [1] = MO_TESW,
- [2] = MO_TESL,
- [4] = MO_UB,
- [5] = MO_TEUW,
-#ifdef TARGET_RISCV64
- [3] = MO_TEQ,
- [6] = MO_TEUL,
-#endif
-};
-#endif
-
#ifdef TARGET_RISCV64
#define CASE_OP_32_64(X) case X: case glue(X, W)
#else
@@ -309,109 +293,6 @@ static void gen_jal(CPURISCVState *env, DisasContext *ctx, int rd,
ctx->base.is_jmp = DISAS_NORETURN;
}
-#ifdef TARGET_RISCV64
-static void gen_load_c(DisasContext *ctx, uint32_t opc, int rd, int rs1,
- target_long imm)
-{
- TCGv t0 = tcg_temp_new();
- TCGv t1 = tcg_temp_new();
- gen_get_gpr(t0, rs1);
- tcg_gen_addi_tl(t0, t0, imm);
- int memop = tcg_memop_lookup[(opc >> 12) & 0x7];
-
- if (memop < 0) {
- gen_exception_illegal(ctx);
- return;
- }
-
- tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop);
- gen_set_gpr(rd, t1);
- tcg_temp_free(t0);
- tcg_temp_free(t1);
-}
-
-static void gen_store_c(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
- target_long imm)
-{
- TCGv t0 = tcg_temp_new();
- TCGv dat = tcg_temp_new();
- gen_get_gpr(t0, rs1);
- tcg_gen_addi_tl(t0, t0, imm);
- gen_get_gpr(dat, rs2);
- int memop = tcg_memop_lookup[(opc >> 12) & 0x7];
-
- if (memop < 0) {
- gen_exception_illegal(ctx);
- return;
- }
-
- tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop);
- tcg_temp_free(t0);
- tcg_temp_free(dat);
-}
-#endif
-
-#ifdef TARGET_RISCV32
-static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd,
- int rs1, target_long imm)
-{
- TCGv t0;
-
- if (!(ctx->flags & TB_FLAGS_FP_ENABLE)) {
- gen_exception_illegal(ctx);
- return;
- }
-
- t0 = tcg_temp_new();
- gen_get_gpr(t0, rs1);
- tcg_gen_addi_tl(t0, t0, imm);
-
- switch (opc) {
- case OPC_RISC_FLW:
- tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEUL);
- /* RISC-V requires NaN-boxing of narrower width floating point values */
- tcg_gen_ori_i64(cpu_fpr[rd], cpu_fpr[rd], 0xffffffff00000000ULL);
- break;
- case OPC_RISC_FLD:
- tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEQ);
- break;
- default:
- gen_exception_illegal(ctx);
- break;
- }
- tcg_temp_free(t0);
-}
-
-static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1,
- int rs2, target_long imm)
-{
- TCGv t0;
-
- if (!(ctx->flags & TB_FLAGS_FP_ENABLE)) {
- gen_exception_illegal(ctx);
- return;
- }
-
- t0 = tcg_temp_new();
- gen_get_gpr(t0, rs1);
- tcg_gen_addi_tl(t0, t0, imm);
-
- switch (opc) {
- case OPC_RISC_FSW:
- tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEUL);
- break;
- case OPC_RISC_FSD:
- tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEQ);
- break;
- default:
- gen_exception_illegal(ctx);
- break;
- }
-
- tcg_temp_free(t0);
-}
-#endif
-
static void gen_set_rm(DisasContext *ctx, int rm)
{
TCGv_i32 t0;
@@ -425,49 +306,6 @@ static void gen_set_rm(DisasContext *ctx, int rm)
tcg_temp_free_i32(t0);
}
-static void decode_RV32_64C0(DisasContext *ctx)
-{
- uint8_t funct3 = extract32(ctx->opcode, 13, 3);
- uint8_t rd_rs2 = GET_C_RS2S(ctx->opcode);
- uint8_t rs1s = GET_C_RS1S(ctx->opcode);
-
- switch (funct3) {
- case 3:
-#if defined(TARGET_RISCV64)
- /* C.LD(RV64/128) -> ld rd', offset[7:3](rs1')*/
- gen_load_c(ctx, OPC_RISC_LD, rd_rs2, rs1s,
- GET_C_LD_IMM(ctx->opcode));
-#else
- /* C.FLW (RV32) -> flw rd', offset[6:2](rs1')*/
- gen_fp_load(ctx, OPC_RISC_FLW, rd_rs2, rs1s,
- GET_C_LW_IMM(ctx->opcode));
-#endif
- break;
- case 7:
-#if defined(TARGET_RISCV64)
- /* C.SD (RV64/128) -> sd rs2', offset[7:3](rs1')*/
- gen_store_c(ctx, OPC_RISC_SD, rs1s, rd_rs2,
- GET_C_LD_IMM(ctx->opcode));
-#else
- /* C.FSW (RV32) -> fsw rs2', offset[6:2](rs1')*/
- gen_fp_store(ctx, OPC_RISC_FSW, rs1s, rd_rs2,
- GET_C_LW_IMM(ctx->opcode));
-#endif
- break;
- }
-}
-
-static void decode_RV32_64C(CPURISCVState *env, DisasContext *ctx)
-{
- uint8_t op = extract32(ctx->opcode, 0, 2);
-
- switch (op) {
- case 0:
- decode_RV32_64C0(ctx);
- break;
- }
-}
-
#define EX_SH(amount) \
static int ex_shift_##amount(int imm) \
{ \
@@ -611,8 +449,7 @@ static void decode_opc(DisasContext *ctx)
} else {
ctx->pc_succ_insn = ctx->base.pc_next + 2;
if (!decode_insn16(ctx, ctx->opcode)) {
- /* fall back to old decoder */
- decode_RV32_64C(ctx->env, ctx);
+ gen_exception_illegal(ctx);
}
}
} else {
--
2.19.1
WARNING: multiple messages have this Message-ID (diff)
From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
To: mjc@sifive.com, sagark@eecs.berkeley.edu, palmer@sifive.com,
kbastian@mail.uni-paderborn.de, Alistair.Francis@wdc.com
Cc: richard.henderson@linaro.org, peer.adelt@hni.uni-paderborn.de,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Subject: [Qemu-riscv] [PATCH v3 33/35] target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
Date: Wed, 31 Oct 2018 14:20:27 +0100 [thread overview]
Message-ID: <20181031132029.4887-34-kbastian@mail.uni-paderborn.de> (raw)
In-Reply-To: <20181031132029.4887-1-kbastian@mail.uni-paderborn.de>
this finally removes the old decoder functions that we carried along
with it.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target/riscv/Makefile.objs | 1 +
target/riscv/insn16-32.decode | 24 ++++
target/riscv/insn16-64.decode | 4 +
target/riscv/insn16.decode | 7 +-
target/riscv/insn_trans/trans_rvc.inc.c | 22 ----
target/riscv/translate.c | 165 +-----------------------
6 files changed, 31 insertions(+), 192 deletions(-)
create mode 100644 target/riscv/insn16-32.decode
diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs
index 515c12b4f8..3086ef0c29 100644
--- a/target/riscv/Makefile.objs
+++ b/target/riscv/Makefile.objs
@@ -6,6 +6,7 @@ decode32-y = $(SRC_PATH)/target/riscv/insn32.decode
decode32-$(TARGET_RISCV64) += $(SRC_PATH)/target/riscv/insn64.decode
decode16-y = $(SRC_PATH)/target/riscv/insn16.decode
+decode16-$(TARGET_RISCV32) += $(SRC_PATH)/target/riscv/insn16-32.decode
decode16-$(TARGET_RISCV64) += $(SRC_PATH)/target/riscv/insn16-64.decode
target/riscv/decode_insn32.inc.c: $(decode32-y) $(DECODETREE)
diff --git a/target/riscv/insn16-32.decode b/target/riscv/insn16-32.decode
new file mode 100644
index 0000000000..e21a701056
--- /dev/null
+++ b/target/riscv/insn16-32.decode
@@ -0,0 +1,24 @@
+#
+# RISC-V translation routines for the RVC Instruction Set.
+#
+# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
+# Bastian Koppelmann, kbastian@mail.uni-paderborn.de
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2 or later, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+# more details.
+#
+# You should have received a copy of the GNU General Public License along with
+# this program. If not, see <http://www.gnu.org/licenses/>.
+
+# This is concatenated with insn16.decode for risc32 targets.
+# All of the fields and formats are there.
+
+# *** RV32C Standard Extension (Quadrant 0) ***
+flw 011 ... ... .. ... 00 @cl_w
+fsw 111 ... ... .. ... 00 @cs_w
diff --git a/target/riscv/insn16-64.decode b/target/riscv/insn16-64.decode
index 5af2e2b072..de97a45acf 100644
--- a/target/riscv/insn16-64.decode
+++ b/target/riscv/insn16-64.decode
@@ -19,6 +19,10 @@
# This is concatenated with insn16.decode for risc64 targets.
# All of the fields and formats are there.
+# *** RV64C Standard Extension (Quadrant 0) ***
+ld 011 ... ... .. ... 00 @cl_d
+sd 111 ... ... .. ... 00 @cs_d
+
# *** RV64C Standard Extension (Quadrant 1) ***
subw 100 1 11 ... 00 ... 01 @cs_2
addw 100 1 11 ... 01 ... 01 @cs_2
diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
index c215867ff9..b075336062 100644
--- a/target/riscv/insn16.decode
+++ b/target/riscv/insn16.decode
@@ -47,10 +47,9 @@
&s imm rs1 rs2 !extern
# Argument sets:
-&cl rs1 rd
&ci imm rd
&ciw nzuimm rd
-&cs rs1 rs2
+&cs_dw uimm rs1 rs2
&cb imm rs1
&cr rd rs2
&c_j imm
@@ -69,8 +68,6 @@
@ciw ... ........ ... .. &ciw nzuimm=%nzuimm_ciw rd=%rs2_3
@cl_d ... ... ... .. ... .. &i imm=%uimm_cl_d rs1=%rs1_3 rd=%rs2_3
@cl_w ... ... ... .. ... .. &i imm=%uimm_cl_w rs1=%rs1_3 rd=%rs2_3
-@cl ... ... ... .. ... .. &cl rs1=%rs1_3 rd=%rs2_3
-@cs ... ... ... .. ... .. &cs rs1=%rs1_3 rs2=%rs2_3
@cs_2 ... ... ... .. ... .. &r rd=%rs1_3 rs1=%rs1_3 rs2=%rs2_3
@cs_d ... ... ... .. ... .. &s imm=%uimm_cl_d rs1=%rs1_3 rs2=%rs2_3
@cs_w ... ... ... .. ... .. &s imm=%uimm_cl_w rs1=%rs1_3 rs2=%rs2_3
@@ -97,10 +94,8 @@
c_addi4spn 000 ........ ... 00 @ciw
fld 001 ... ... .. ... 00 @cl_d
lw 010 ... ... .. ... 00 @cl_w
-c_flw_ld 011 --- ... -- ... 00 @cl #Note: Must parse uimm manually
fsd 101 ... ... .. ... 00 @cs_d
sw 110 ... ... .. ... 00 @cs_w
-c_fsw_sd 111 --- ... -- ... 00 @cs #Note: Must parse uimm manually
# *** RV64C Standard Extension (Quadrant 1) ***
c_addi 000 . ..... ..... 01 @ci
diff --git a/target/riscv/insn_trans/trans_rvc.inc.c b/target/riscv/insn_trans/trans_rvc.inc.c
index d932bfd3e0..f521daf32e 100644
--- a/target/riscv/insn_trans/trans_rvc.inc.c
+++ b/target/riscv/insn_trans/trans_rvc.inc.c
@@ -28,28 +28,6 @@ static bool trans_c_addi4spn(DisasContext *ctx, arg_c_addi4spn *a)
return trans_addi(ctx, &arg);
}
-static bool trans_c_flw_ld(DisasContext *ctx, arg_c_flw_ld *a)
-{
-#ifdef TARGET_RISCV32
- /* C.FLW ( RV32FC-only ) */
- return false;
-#else
- /* C.LD ( RV64C/RV128C-only ) */
- return false;
-#endif
-}
-
-static bool trans_c_fsw_sd(DisasContext *ctx, arg_c_fsw_sd *a)
-{
-#ifdef TARGET_RISCV32
- /* C.FSW ( RV32FC-only ) */
- return false;
-#else
- /* C.SD ( RV64C/RV128C-only ) */
- return false;
-#endif
-}
-
static bool trans_c_addi(DisasContext *ctx, arg_c_addi *a)
{
if (a->imm == 0) {
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 56b650a9d7..1d4f848e9a 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -55,22 +55,6 @@ typedef struct DisasContext {
CPURISCVState *env;
} DisasContext;
-#ifdef TARGET_RISCV64
-/* convert riscv funct3 to qemu memop for load/store */
-static const int tcg_memop_lookup[8] = {
- [0 ... 7] = -1,
- [0] = MO_SB,
- [1] = MO_TESW,
- [2] = MO_TESL,
- [4] = MO_UB,
- [5] = MO_TEUW,
-#ifdef TARGET_RISCV64
- [3] = MO_TEQ,
- [6] = MO_TEUL,
-#endif
-};
-#endif
-
#ifdef TARGET_RISCV64
#define CASE_OP_32_64(X) case X: case glue(X, W)
#else
@@ -309,109 +293,6 @@ static void gen_jal(CPURISCVState *env, DisasContext *ctx, int rd,
ctx->base.is_jmp = DISAS_NORETURN;
}
-#ifdef TARGET_RISCV64
-static void gen_load_c(DisasContext *ctx, uint32_t opc, int rd, int rs1,
- target_long imm)
-{
- TCGv t0 = tcg_temp_new();
- TCGv t1 = tcg_temp_new();
- gen_get_gpr(t0, rs1);
- tcg_gen_addi_tl(t0, t0, imm);
- int memop = tcg_memop_lookup[(opc >> 12) & 0x7];
-
- if (memop < 0) {
- gen_exception_illegal(ctx);
- return;
- }
-
- tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop);
- gen_set_gpr(rd, t1);
- tcg_temp_free(t0);
- tcg_temp_free(t1);
-}
-
-static void gen_store_c(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
- target_long imm)
-{
- TCGv t0 = tcg_temp_new();
- TCGv dat = tcg_temp_new();
- gen_get_gpr(t0, rs1);
- tcg_gen_addi_tl(t0, t0, imm);
- gen_get_gpr(dat, rs2);
- int memop = tcg_memop_lookup[(opc >> 12) & 0x7];
-
- if (memop < 0) {
- gen_exception_illegal(ctx);
- return;
- }
-
- tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop);
- tcg_temp_free(t0);
- tcg_temp_free(dat);
-}
-#endif
-
-#ifdef TARGET_RISCV32
-static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd,
- int rs1, target_long imm)
-{
- TCGv t0;
-
- if (!(ctx->flags & TB_FLAGS_FP_ENABLE)) {
- gen_exception_illegal(ctx);
- return;
- }
-
- t0 = tcg_temp_new();
- gen_get_gpr(t0, rs1);
- tcg_gen_addi_tl(t0, t0, imm);
-
- switch (opc) {
- case OPC_RISC_FLW:
- tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEUL);
- /* RISC-V requires NaN-boxing of narrower width floating point values */
- tcg_gen_ori_i64(cpu_fpr[rd], cpu_fpr[rd], 0xffffffff00000000ULL);
- break;
- case OPC_RISC_FLD:
- tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEQ);
- break;
- default:
- gen_exception_illegal(ctx);
- break;
- }
- tcg_temp_free(t0);
-}
-
-static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1,
- int rs2, target_long imm)
-{
- TCGv t0;
-
- if (!(ctx->flags & TB_FLAGS_FP_ENABLE)) {
- gen_exception_illegal(ctx);
- return;
- }
-
- t0 = tcg_temp_new();
- gen_get_gpr(t0, rs1);
- tcg_gen_addi_tl(t0, t0, imm);
-
- switch (opc) {
- case OPC_RISC_FSW:
- tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEUL);
- break;
- case OPC_RISC_FSD:
- tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEQ);
- break;
- default:
- gen_exception_illegal(ctx);
- break;
- }
-
- tcg_temp_free(t0);
-}
-#endif
-
static void gen_set_rm(DisasContext *ctx, int rm)
{
TCGv_i32 t0;
@@ -425,49 +306,6 @@ static void gen_set_rm(DisasContext *ctx, int rm)
tcg_temp_free_i32(t0);
}
-static void decode_RV32_64C0(DisasContext *ctx)
-{
- uint8_t funct3 = extract32(ctx->opcode, 13, 3);
- uint8_t rd_rs2 = GET_C_RS2S(ctx->opcode);
- uint8_t rs1s = GET_C_RS1S(ctx->opcode);
-
- switch (funct3) {
- case 3:
-#if defined(TARGET_RISCV64)
- /* C.LD(RV64/128) -> ld rd', offset[7:3](rs1')*/
- gen_load_c(ctx, OPC_RISC_LD, rd_rs2, rs1s,
- GET_C_LD_IMM(ctx->opcode));
-#else
- /* C.FLW (RV32) -> flw rd', offset[6:2](rs1')*/
- gen_fp_load(ctx, OPC_RISC_FLW, rd_rs2, rs1s,
- GET_C_LW_IMM(ctx->opcode));
-#endif
- break;
- case 7:
-#if defined(TARGET_RISCV64)
- /* C.SD (RV64/128) -> sd rs2', offset[7:3](rs1')*/
- gen_store_c(ctx, OPC_RISC_SD, rs1s, rd_rs2,
- GET_C_LD_IMM(ctx->opcode));
-#else
- /* C.FSW (RV32) -> fsw rs2', offset[6:2](rs1')*/
- gen_fp_store(ctx, OPC_RISC_FSW, rs1s, rd_rs2,
- GET_C_LW_IMM(ctx->opcode));
-#endif
- break;
- }
-}
-
-static void decode_RV32_64C(CPURISCVState *env, DisasContext *ctx)
-{
- uint8_t op = extract32(ctx->opcode, 0, 2);
-
- switch (op) {
- case 0:
- decode_RV32_64C0(ctx);
- break;
- }
-}
-
#define EX_SH(amount) \
static int ex_shift_##amount(int imm) \
{ \
@@ -611,8 +449,7 @@ static void decode_opc(DisasContext *ctx)
} else {
ctx->pc_succ_insn = ctx->base.pc_next + 2;
if (!decode_insn16(ctx, ctx->opcode)) {
- /* fall back to old decoder */
- decode_RV32_64C(ctx->env, ctx);
+ gen_exception_illegal(ctx);
}
}
} else {
--
2.19.1
next prev parent reply other threads:[~2018-10-31 13:22 UTC|newest]
Thread overview: 140+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-31 13:19 [Qemu-devel] [PATCH v3 00/35] target/riscv: Convert to decodetree Bastian Koppelmann
2018-10-31 13:19 ` [Qemu-riscv] " Bastian Koppelmann
2018-10-31 13:19 ` [Qemu-devel] [PATCH v3 01/35] target/riscv: Move CPURISCVState pointer to DisasContext Bastian Koppelmann
2018-10-31 13:19 ` [Qemu-riscv] " Bastian Koppelmann
2018-10-31 17:07 ` [Qemu-devel] " Richard Henderson
2018-10-31 17:07 ` [Qemu-riscv] " Richard Henderson
2018-10-31 20:14 ` [Qemu-devel] " Alistair Francis
2018-10-31 20:14 ` [Qemu-riscv] " Alistair Francis
2018-10-31 13:19 ` [Qemu-devel] [PATCH v3 02/35] target/riscv: Activate decodetree and implemnt LUI & AUIPC Bastian Koppelmann
2018-10-31 13:19 ` [Qemu-riscv] " Bastian Koppelmann
2018-10-31 20:20 ` [Qemu-devel] " Alistair
2018-10-31 20:20 ` [Qemu-riscv] " Alistair
2018-10-31 13:19 ` [Qemu-devel] [PATCH v3 03/35] target/riscv: Convert RVXI branch insns to decodetree Bastian Koppelmann
2018-10-31 13:19 ` [Qemu-riscv] " Bastian Koppelmann
2018-10-31 17:11 ` [Qemu-devel] " Richard Henderson
2018-10-31 17:11 ` [Qemu-riscv] " Richard Henderson
2018-10-31 13:19 ` [Qemu-devel] [PATCH v3 04/35] target/riscv: Convert RV32I load/store " Bastian Koppelmann
2018-10-31 13:19 ` [Qemu-riscv] " Bastian Koppelmann
2018-10-31 13:19 ` [Qemu-devel] [PATCH v3 05/35] target/riscv: Convert RV64I " Bastian Koppelmann
2018-10-31 13:19 ` [Qemu-riscv] " Bastian Koppelmann
2018-10-31 17:14 ` [Qemu-devel] " Richard Henderson
2018-10-31 17:14 ` [Qemu-riscv] " Richard Henderson
2018-10-31 20:26 ` [Qemu-devel] " Alistair
2018-10-31 20:26 ` [Qemu-riscv] " Alistair
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 06/35] target/riscv: Convert RVXI arithmetic " Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-riscv] " Bastian Koppelmann
2018-10-31 17:15 ` [Qemu-devel] " Richard Henderson
2018-10-31 17:15 ` [Qemu-riscv] " Richard Henderson
2018-10-31 20:29 ` [Qemu-devel] " Alistair
2018-10-31 20:29 ` [Qemu-riscv] " Alistair
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 07/35] target/riscv: Convert RVXI fence " Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-riscv] " Bastian Koppelmann
2018-10-31 20:30 ` [Qemu-devel] " Alistair
2018-10-31 20:30 ` [Qemu-riscv] " Alistair
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 08/35] target/riscv: Convert RVXI csr " Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-riscv] " Bastian Koppelmann
2018-10-31 20:46 ` [Qemu-devel] " Alistair
2018-10-31 20:46 ` [Qemu-riscv] " Alistair
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 09/35] target/riscv: Convert RVXM " Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-riscv] " Bastian Koppelmann
2018-10-31 20:38 ` [Qemu-devel] " Alistair
2018-10-31 20:38 ` [Qemu-riscv] " Alistair
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 10/35] target/riscv: Convert RV32A " Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-riscv] " Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 11/35] target/riscv: Convert RV64A " Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-riscv] " Bastian Koppelmann
2018-10-31 20:49 ` [Qemu-devel] " Alistair
2018-10-31 20:49 ` [Qemu-riscv] " Alistair
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 12/35] target/riscv: Convert RV32F " Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-riscv] " Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 13/35] target/riscv: Convert RV64F " Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-riscv] " Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 14/35] target/riscv: Convert RV32D " Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-riscv] " Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 15/35] target/riscv: Convert RV64D " Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-riscv] " Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 16/35] target/riscv: Convert RV priv " Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-riscv] " Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 17/35] target/riscv: Convert quadrant 0 of RVXC " Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-riscv] " Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 18/35] target/riscv: Convert quadrant 1 " Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-riscv] " Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 19/35] target/riscv: Convert quadrant 2 " Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-riscv] " Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 20/35] target/riscv: Remove gen_jalr() Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-riscv] " Bastian Koppelmann
2018-10-31 20:50 ` [Qemu-devel] " Alistair
2018-10-31 20:50 ` [Qemu-riscv] " Alistair
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 21/35] target/riscv: Remove manual decoding from gen_branch() Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-riscv] " Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 22/35] target/riscv: Remove manual decoding from gen_load() Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-riscv] " Bastian Koppelmann
2018-10-31 22:09 ` [Qemu-devel] " Richard Henderson
2018-10-31 22:09 ` [Qemu-riscv] " Richard Henderson
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 23/35] target/riscv: Remove manual decoding from gen_store() Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-riscv] " Bastian Koppelmann
2018-10-31 22:09 ` [Qemu-devel] " Richard Henderson
2018-10-31 22:09 ` [Qemu-riscv] " Richard Henderson
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-riscv] " Bastian Koppelmann
2018-10-31 22:18 ` [Qemu-devel] " Richard Henderson
2018-10-31 22:18 ` [Qemu-riscv] " Richard Henderson
2019-01-11 13:10 ` [Qemu-devel] " Bastian Koppelmann
2019-01-11 13:10 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-11 21:00 ` Richard Henderson
2019-01-11 21:00 ` [Qemu-riscv] " Richard Henderson
2019-01-18 12:00 ` Bastian Koppelmann
2019-01-18 12:00 ` [Qemu-riscv] " Bastian Koppelmann
2018-10-31 22:26 ` Richard Henderson
2018-10-31 22:26 ` [Qemu-riscv] " Richard Henderson
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 25/35] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-riscv] " Bastian Koppelmann
2018-10-31 20:44 ` [Qemu-devel] " Alistair Francis
2018-10-31 20:44 ` [Qemu-riscv] " Alistair Francis
2018-10-31 22:27 ` Richard Henderson
2018-10-31 22:27 ` [Qemu-riscv] " Richard Henderson
2018-10-31 22:26 ` Richard Henderson
2018-10-31 22:26 ` [Qemu-riscv] " Richard Henderson
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 26/35] target/riscv: Remove shift and slt insn manual decoding Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-riscv] " Bastian Koppelmann
2018-10-31 22:38 ` [Qemu-devel] " Richard Henderson
2018-10-31 22:38 ` [Qemu-riscv] " Richard Henderson
2018-11-01 15:59 ` [Qemu-devel] " Palmer Dabbelt
2018-11-01 15:59 ` [Qemu-riscv] " Palmer Dabbelt
2018-11-05 17:00 ` [Qemu-devel] " Bastian Koppelmann
2018-11-05 17:00 ` [Qemu-riscv] " Bastian Koppelmann
2018-11-07 0:56 ` Palmer Dabbelt
2018-11-07 0:56 ` [Qemu-riscv] " Palmer Dabbelt
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 27/35] target/riscv: Remove manual decoding of RV32/64M insn Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-riscv] " Bastian Koppelmann
2018-10-31 22:39 ` [Qemu-devel] " Richard Henderson
2018-10-31 22:39 ` [Qemu-riscv] " Richard Henderson
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 28/35] target/riscv: Rename trans_arith to gen_arith Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-riscv] " Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 29/35] target/riscv: Remove gen_system() Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-riscv] " Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 30/35] target/riscv: Remove decode_RV32_64G() Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-riscv] " Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 31/35] target/riscv: Convert @cs_2 insns to share translation functions Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-riscv] " Bastian Koppelmann
2018-10-31 22:42 ` [Qemu-devel] " Richard Henderson
2018-10-31 22:42 ` [Qemu-riscv] " Richard Henderson
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 32/35] target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-riscv] " Bastian Koppelmann
2018-10-31 22:43 ` [Qemu-devel] " Richard Henderson
2018-10-31 22:43 ` [Qemu-riscv] " Richard Henderson
2018-10-31 13:20 ` Bastian Koppelmann [this message]
2018-10-31 13:20 ` [Qemu-riscv] [PATCH v3 33/35] target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64 Bastian Koppelmann
2018-10-31 22:45 ` [Qemu-devel] " Richard Henderson
2018-10-31 22:45 ` [Qemu-riscv] " Richard Henderson
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 34/35] target/riscv: Splice remaining compressed insn pairs " Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-riscv] " Bastian Koppelmann
2018-10-31 22:47 ` [Qemu-devel] " Richard Henderson
2018-10-31 22:47 ` [Qemu-riscv] " Richard Henderson
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 35/35] target/riscv: Remaining rvc insn reuse 32 bit translators Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-riscv] " Bastian Koppelmann
2018-10-31 22:49 ` [Qemu-devel] " Richard Henderson
2018-10-31 22:49 ` [Qemu-riscv] " Richard Henderson
2018-11-02 8:48 ` [Qemu-devel] [PATCH v3 00/35] target/riscv: Convert to decodetree no-reply
2018-11-02 8:48 ` [Qemu-riscv] " no-reply
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20181031132029.4887-34-kbastian@mail.uni-paderborn.de \
--to=kbastian@mail.uni-paderborn.de \
--cc=Alistair.Francis@wdc.com \
--cc=mjc@sifive.com \
--cc=palmer@sifive.com \
--cc=peer.adelt@hni.uni-paderborn.de \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
--cc=richard.henderson@linaro.org \
--cc=sagark@eecs.berkeley.edu \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.