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From: Manasi Navare <manasi.d.navare@intel.com>
To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Cc: Manasi Navare <manasi.d.navare@intel.com>,
	Anusha Srivatsa <anusha.srivatsa@intel.com>,
	Gaurav K Singh <gaurav.k.singh@intel.com>
Subject: [PATCH v9 12/24] drm/i915/dp: Enable/Disable DSC in DP Sink
Date: Tue, 13 Nov 2018 17:52:20 -0800	[thread overview]
Message-ID: <20181114015232.21952-13-manasi.d.navare@intel.com> (raw)
In-Reply-To: <20181114015232.21952-1-manasi.d.navare@intel.com>

From: Gaurav K Singh <gaurav.k.singh@intel.com>

This patch enables decompression support in sink device
before link training and disables the same during the
DDI disabling.

v3 (From manasi):
* Pass bool state to enable/disable (Ville)
v2:(From Manasi)
* Change the enable/disable function to take crtc_state
instead of intel_dp as an argument (Manasi)
* Use the compression_enable flag as part of crtc_state (Manasi)

Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c |  5 +++++
 drivers/gpu/drm/i915/intel_dp.c  | 16 ++++++++++++++++
 drivers/gpu/drm/i915/intel_drv.h |  3 +++
 3 files changed, 24 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 4913bbdac843..c7d417e6262f 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -3134,6 +3134,8 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
 	intel_ddi_init_dp_buf_reg(encoder);
 	if (!is_mst)
 		intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
+	intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
+					      true);
 	intel_dp_start_link_train(intel_dp);
 	if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
 		intel_dp_stop_link_train(intel_dp);
@@ -3478,6 +3480,9 @@ static void intel_disable_ddi_dp(struct intel_encoder *encoder,
 	intel_edp_drrs_disable(intel_dp, old_crtc_state);
 	intel_psr_disable(intel_dp, old_crtc_state);
 	intel_edp_backlight_off(old_conn_state);
+	/* Disable the decompression in DP Sink */
+	intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
+					      false);
 }
 
 static void intel_disable_ddi_hdmi(struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 0bdaa6e848a9..b43a77bf42df 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2856,6 +2856,22 @@ static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
 		intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
 }
 
+void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
+					   const struct intel_crtc_state *crtc_state,
+					   bool enable)
+{
+	int ret;
+
+	if (!crtc_state->dsc_params.compression_enable)
+		return;
+
+	ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE,
+				 enable ? DP_DECOMPRESSION_EN : 0);
+	if (ret < 0)
+		DRM_DEBUG_KMS("Failed to %s sink decompression state\n",
+			      enable ? "enable" : "disable");
+}
+
 /* If the sink supports it, try to set the power state appropriately */
 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
 {
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index d6466c401358..5b53fc262b91 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1796,6 +1796,9 @@ void intel_dp_stop_link_train(struct intel_dp *intel_dp);
 int intel_dp_retrain_link(struct intel_encoder *encoder,
 			  struct drm_modeset_acquire_ctx *ctx);
 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
+void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
+					   const struct intel_crtc_state *crtc_state,
+					   bool enable);
 void intel_dp_encoder_reset(struct drm_encoder *encoder);
 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
-- 
2.19.1

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  parent reply	other threads:[~2018-11-14  1:52 UTC|newest]

Thread overview: 42+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-11-14  1:52 [PATCH v9 00/24] Remaining DSC + FEC patches Manasi Navare
2018-11-14  1:52 ` [PATCH v9 01/24] drm/dsc: Modify DRM helper to return complete DSC color depth capabilities Manasi Navare
2018-11-19 19:43   ` Ville Syrjälä
2018-11-19 20:10     ` Manasi Navare
2018-11-19 20:33       ` Ville Syrjälä
2018-11-19 22:11         ` Manasi Navare
2018-11-14  1:52 ` [PATCH v9 02/24] drm/dsc: Define Display Stream Compression PPS infoframe Manasi Navare
2018-11-14  1:52 ` [PATCH v9 03/24] drm/dsc: Define VESA Display Stream Compression Capabilities Manasi Navare
2018-11-14  1:52 ` [PATCH v9 04/24] drm/dsc: Define Rate Control values that do not change over configurations Manasi Navare
2018-11-14  1:52 ` [PATCH v9 05/24] drm/dsc: Add helpers for DSC picture parameter set infoframes Manasi Navare
2018-11-14  1:52 ` [PATCH v9 06/24] drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants Manasi Navare
2018-11-14  1:52 ` [PATCH v9 07/24] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state Manasi Navare
2018-11-14  1:52 ` [PATCH v9 08/24] drm/i915/dp: Compute DSC pipe config in atomic check Manasi Navare
2018-11-19 20:11   ` Ville Syrjälä
2018-11-19 21:54     ` Manasi Navare
2018-11-14  1:52 ` [PATCH v9 09/24] drm/i915/dp: Do not enable PSR2 if DSC is enabled Manasi Navare
2018-11-14  1:52 ` [PATCH v9 10/24] drm/i915/dsc: Define & Compute VESA DSC params Manasi Navare
2018-11-14  1:52 ` [PATCH v9 11/24] drm/i915/dsc: Compute Rate Control parameters for DSC Manasi Navare
2018-11-14  1:52 ` Manasi Navare [this message]
2018-11-14  1:52 ` [PATCH v9 13/24] drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI Manasi Navare
2018-11-14  1:52 ` [PATCH v9 14/24] drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling Manasi Navare
2018-11-19 20:17   ` Ville Syrjälä
2018-11-14  1:52 ` [PATCH v9 15/24] drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs Manasi Navare
2018-11-14  1:52 ` [PATCH v9 16/24] drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes Manasi Navare
2018-11-14  1:52 ` [PATCH v9 17/24] drm/i915/dp: Configure Display stream splitter registers during DSC enable Manasi Navare
2018-11-14  1:52 ` [PATCH v9 18/24] drm/i915/dp: Disable DSC in source by disabling DSS CTL bits Manasi Navare
2018-11-14  1:52 ` [PATCH v9 19/24] drm/i915/dsc: Enable and disable appropriate power wells for VDSC Manasi Navare
2018-11-14  1:52 ` [PATCH v9 20/24] drm/i915/dsc: Add Per connector debugfs node for DSC support/enable Manasi Navare
2018-11-16  1:39   ` Manasi Navare
2018-11-19 20:27     ` Ville Syrjälä
2018-11-19 22:28       ` Manasi Navare
2018-11-14  1:52 ` [PATCH v9 21/24] i915/dp/fec: Add fec_enable to the crtc state Manasi Navare
2018-11-14  1:52 ` [PATCH v9 22/24] drm/i915/fec: Set FEC_READY in FEC_CONFIGURATION Manasi Navare
2018-11-19 20:19   ` Ville Syrjälä
2018-11-20  0:43     ` Manasi Navare
2018-11-20 17:13     ` Manasi Navare
2018-11-14  1:52 ` [PATCH v9 23/24] i915/dp/fec: Configure the Forward Error Correction bits Manasi Navare
2018-11-14  1:52 ` [PATCH v9 24/24] drm/i915/fec: Disable FEC state Manasi Navare
2018-11-14  2:14 ` ✗ Fi.CI.CHECKPATCH: warning for Remaining DSC + FEC patches Patchwork
2018-11-14  2:23 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-11-14  4:45 ` ✓ Fi.CI.BAT: success " Patchwork
2018-11-14  7:51 ` ✓ Fi.CI.IGT: " Patchwork

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