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From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
To: linux-amlogic@lists.infradead.org, khilman@baylibre.com
Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH 3/6] ARM: dts: meson8b: add the temperature calibration data for the SAR ADC
Date: Sat, 12 Jan 2019 14:06:46 +0100	[thread overview]
Message-ID: <20190112130649.23838-4-martin.blumenstingl@googlemail.com> (raw)
In-Reply-To: <20190112130649.23838-1-martin.blumenstingl@googlemail.com>

The SAR ADC can measure the chip temperature of the SoC. This only
works if the chip is calibrated and if the calibration data is written
to the correct registers. The calibration data is stored in the upper
two bytes of eFuse offset 0x1f4.

This adds the eFuse cell for the temperature calibration data and
passes it to the SAR ADC. We also need to pass the HHI sysctrl node to
the SAR ADC because the 4th TSC (temperature sensor calibration
coefficient) bit is stored in the HHI region (unlike bits [3:0] which
are stored directly inside the SAR ADC's register area).

On boards that have the SAR ADC enabled channel 8 can be used to
measure the chip temperature.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
 arch/arm/boot/dts/meson8b.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
index 57c2a3678110..3bd68cf8f6c0 100644
--- a/arch/arm/boot/dts/meson8b.dtsi
+++ b/arch/arm/boot/dts/meson8b.dtsi
@@ -414,6 +414,11 @@
 	compatible = "amlogic,meson8b-efuse";
 	clocks = <&clkc CLKID_EFUSE>;
 	clock-names = "core";
+
+	temperature_calib: calib@1f4 {
+		/* only the upper two bytes are relevant */
+		reg = <0x1f4 0x4>;
+	};
 };
 
 &ethmac {
@@ -504,6 +509,9 @@
 	clocks = <&clkc CLKID_XTAL>,
 		<&clkc CLKID_SAR_ADC>;
 	clock-names = "clkin", "core";
+	amlogic,hhi-sysctrl = <&hhi>;
+	nvmem-cells = <&temperature_calib>;
+	nvmem-cell-names = "temperature_calib";
 };
 
 &sdio {
-- 
2.20.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

WARNING: multiple messages have this Message-ID (diff)
From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
To: linux-amlogic@lists.infradead.org, khilman@baylibre.com
Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH 3/6] ARM: dts: meson8b: add the temperature calibration data for the SAR ADC
Date: Sat, 12 Jan 2019 14:06:46 +0100	[thread overview]
Message-ID: <20190112130649.23838-4-martin.blumenstingl@googlemail.com> (raw)
In-Reply-To: <20190112130649.23838-1-martin.blumenstingl@googlemail.com>

The SAR ADC can measure the chip temperature of the SoC. This only
works if the chip is calibrated and if the calibration data is written
to the correct registers. The calibration data is stored in the upper
two bytes of eFuse offset 0x1f4.

This adds the eFuse cell for the temperature calibration data and
passes it to the SAR ADC. We also need to pass the HHI sysctrl node to
the SAR ADC because the 4th TSC (temperature sensor calibration
coefficient) bit is stored in the HHI region (unlike bits [3:0] which
are stored directly inside the SAR ADC's register area).

On boards that have the SAR ADC enabled channel 8 can be used to
measure the chip temperature.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
 arch/arm/boot/dts/meson8b.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
index 57c2a3678110..3bd68cf8f6c0 100644
--- a/arch/arm/boot/dts/meson8b.dtsi
+++ b/arch/arm/boot/dts/meson8b.dtsi
@@ -414,6 +414,11 @@
 	compatible = "amlogic,meson8b-efuse";
 	clocks = <&clkc CLKID_EFUSE>;
 	clock-names = "core";
+
+	temperature_calib: calib@1f4 {
+		/* only the upper two bytes are relevant */
+		reg = <0x1f4 0x4>;
+	};
 };
 
 &ethmac {
@@ -504,6 +509,9 @@
 	clocks = <&clkc CLKID_XTAL>,
 		<&clkc CLKID_SAR_ADC>;
 	clock-names = "clkin", "core";
+	amlogic,hhi-sysctrl = <&hhi>;
+	nvmem-cells = <&temperature_calib>;
+	nvmem-cell-names = "temperature_calib";
 };
 
 &sdio {
-- 
2.20.1


_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic

  parent reply	other threads:[~2019-01-12 13:07 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-01-12 13:06 [PATCH 0/6] ARM: dts: meson: chip temperature (hwmon) support Martin Blumenstingl
2019-01-12 13:06 ` Martin Blumenstingl
2019-01-12 13:06 ` [PATCH 1/6] ARM: dts: meson8m2: use the Meson8m2 specific SAR ADC compatible Martin Blumenstingl
2019-01-12 13:06   ` Martin Blumenstingl
2019-01-12 13:06 ` [PATCH 2/6] ARM: dts: meson8: add the temperature calibration data for the SAR ADC Martin Blumenstingl
2019-01-12 13:06   ` Martin Blumenstingl
2019-01-12 13:06 ` Martin Blumenstingl [this message]
2019-01-12 13:06   ` [PATCH 3/6] ARM: dts: meson8b: " Martin Blumenstingl
2019-01-12 13:06 ` [PATCH 4/6] ARM: dts: meson8b: ec100: add iio-hwmon for the chip temperature Martin Blumenstingl
2019-01-12 13:06   ` Martin Blumenstingl
2019-01-12 13:06 ` [PATCH 5/6] ARM: dts: meson8b: odroidc1: " Martin Blumenstingl
2019-01-12 13:06   ` Martin Blumenstingl
2019-01-12 13:06 ` [PATCH 6/6] ARM: dts: meson8m2: mxiii-plus: " Martin Blumenstingl
2019-01-12 13:06   ` Martin Blumenstingl
2019-01-17 20:26 ` [PATCH 0/6] ARM: dts: meson: chip temperature (hwmon) support Kevin Hilman
2019-01-17 20:26   ` Kevin Hilman
2019-01-17 20:29   ` Martin Blumenstingl
2019-01-17 20:29     ` Martin Blumenstingl
2019-01-17 21:04     ` Kevin Hilman
2019-01-17 21:04       ` Kevin Hilman

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