[PATCH v3 5/8] drm/i915: Bump gen4+ fb stride limit to 256KiB

From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH v3 5/8] drm/i915: Bump gen4+ fb stride limit to 256KiB
Date: Fri, 18 Jan 2019 17:27:17 +0200	[thread overview]
Message-ID: <20190118152720.24643-6-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20190118152720.24643-1-ville.syrjala@linux.intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

With gtt remapping plugged in we can simply raise the stride
limit on gen4+. Let's just arbitraily pick 256 KiB as the limit.

No remapping CCS because the virtual address of each page actually
matters due to the new hash mode
(WaCompressedResourceDisplayNewHashMode:skl,kbl etc.), and no remapping
on gen2/3 due to lack of fence on the remapped vma.

v2: Rebase due to is_ccs_modifier()

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 86847cee833a..f7c4456220cd 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2470,6 +2470,19 @@ static
 u32 intel_fb_max_stride(struct drm_i915_private *dev_priv,
 			u32 pixel_format, u64 modifier)
 {
+	/*
+	 * Arbitrary limit for gen4+. We can deal with any page
+	 * aligned stride via GTT remapping. Gen2/3 need a fence
+	 * for tiled scanout which the remapped vma won't have,
+	 * so we don't allow remapping on those platforms.
+	 *
+	 * Also the new hash mode we use for CCS isn't compatible
+	 * with remapping as the virtual address of the pages
+	 * affects the compressed data.
+	 */
+	if (INTEL_GEN(dev_priv) >= 4 && !is_ccs_modifier(modifier))
+		return 256*1024;
+
 	return intel_plane_fb_max_stride(dev_priv, pixel_format, modifier);
 }
 
-- 
2.19.2

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