From: Priit Laes <plaes@plaes.org>
To: "Jernej Škrabec" <jernej.skrabec@siol.net>
Cc: maxime.ripard@bootlin.com, wens@csie.org, robh+dt@kernel.org,
mturquette@baylibre.com, sboyd@kernel.org, airlied@linux.ie,
architt@codeaurora.org, a.hajda@samsung.com,
Laurent.pinchart@ideasonboard.com, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
dri-devel@lists.freedesktop.org, linux-sunxi@googlegroups.com
Subject: Re: [linux-sunxi] [PATCH v3 02/28] clk: sunxi-ng: Adjust MP clock parent rate when allowed
Date: Mon, 21 Jan 2019 13:34:33 +0000 [thread overview]
Message-ID: <20190121133433.lryqz7ivrj5cxu3g@plaes.org> (raw)
In-Reply-To: <20190121083729.7qsmj7drxvmnjoye@plaes.org>
On Mon, Jan 21, 2019 at 08:37:29AM +0000, Priit Laes wrote:
> On Fri, Jan 18, 2019 at 10:51:10PM +0100, Jernej Škrabec wrote:
> > Dne četrtek, 17. januar 2019 ob 08:24:02 CET je Priit Laes napisal(a):
> > > On Wed, Jan 16, 2019 at 06:00:32PM +0100, Jernej Škrabec wrote:
> > > > Dne sreda, 16. januar 2019 ob 13:09:58 CET je Priit Laes napisal(a):
> > > > > On Thu, Jan 10, 2019 at 06:10:59PM +0100, Jernej Škrabec wrote:
> > > > > > Dne četrtek, 10. januar 2019 ob 10:15:48 CET je Priit Laes napisal(a):
> > > > > > > On Sun, Nov 04, 2018 at 07:26:39PM +0100, Jernej Skrabec wrote:
> > > > > > > > Currently MP clocks don't consider adjusting parent rate even if
> > > > > > > > they
> > > > > > > > are allowed to do so. Such behaviour considerably lowers amount of
> > > > > > > > possible rates, which is very inconvenient when such clock is used
> > > > > > > > for
> > > > > > > > pixel clock, for example.
> > > > > > > >
> > > > > > > > In order to improve the situation, adjusting parent rate is
> > > > > > > > considered
> > > > > > > > when allowed.
> > > > > > > >
> > > > > > > > This code is inspired by clk_divider_bestdiv() function, which
> > > > > > > > does
> > > > > > > > basically the same thing for different clock type.
> > > > > > >
> > > > > > > This patch seems to break the eMMC support on Olinuxino-Lime2-eMMC
> > > > > > > boards:
> > > > > > >
> > > > > > > EXT4-fs (mmcblk1p4): INFO: recovery required on readonly filesystem
> > > > > > > EXT4-fs (mmcblk1p4): write access will be enabled during recovery
> > > > > > > sunxi-mmc 1c11000.mmc: data error, sending stop command
> > > > > > > sunxi-mmc 1c11000.mmc: send stop command failed
> > > > > >
> > > > > > I'm not familiar with A20. What is interesting is that emmc clocks
> > > > > > don't
> > > > > > have CLK_SET_RATE_PARENT flag set, so you shouldn't see any
> > > > > > difference.
> > > > > >
> > > > > > Can you post content of clk_summary with and without this patch?
> > > > >
> > > > > In both cases I booted from FEL with rootfs on sdcard and tried to mount
> > > > > partition from eMMC to /mnt. With your patch, last step it fails.
> > > > >
> > > > > pre-patch working:
> > > > > pll-ddr-other[768MHz] -> mmc2[512MHz]. (For some reason ahb-mmc2 is
> > > > > off?)
> > > > >
> > > > > post-patch not working:
> > > > > pll-periph[600MHz] -> mmc2[500Mhz], (ahb-mmc2 is enabled)
> > > > >
> > > > > Also, attached the logs.
> > > >
> > > > Thanks. Just one more request. Can you enable debug messages in mmc
> > > > driver?
> > > > I'm interested in output of this line:
> > > >
> > > > dev_dbg(mmc_dev(mmc), "setting clk to %d, rounded %ld\n",
> > > >
> > > > clock, rate);
> > >
> > > 1c11000 is eMMC:
> > > [snip]
> > > [ 1.961644] sunxi-mmc 1c11000.mmc: setting clk to 400000, rounded 400000
> > > [ 2.004091] sunxi-mmc 1c11000.mmc: setting clk to 400000, rounded 400000
> > > [ 2.020296] sunxi-mmc 1c11000.mmc: setting clk to 400000, rounded 400000
> > > [ 2.039917] sunxi-mmc 1c11000.mmc: setting clk to 400000, rounded 400000
> > > [ 2.047847] sunxi-mmc 1c11000.mmc: setting clk to 400000, rounded 400000
> > > [ 2.055053] sunxi-mmc 1c11000.mmc: setting clk to 400000, rounded 400000
> > > [ 2.065256] sunxi-mmc 1c11000.mmc: setting clk to 400000, rounded 400000
> > > [ 2.092351] sunxi-mmc 1c11000.mmc: setting clk to 400000, rounded 400000
> > > [ 2.168725] sunxi-mmc 1c11000.mmc: setting clk to 400000, rounded 400000
> > > [ 2.189403] sunxi-mmc 1c11000.mmc: setting clk to 52000000, rounded
> > > 52000000 [ 2.203340] sunxi-mmc 1c11000.mmc: setting clk to 52000000,
> > > rounded 52000000 [ 2.211412] sunxi-mmc 1c11000.mmc: setting clk to
> > > 52000000, rounded 52000000 [ 4.967865] sunxi-mmc 1c11000.mmc: setting
> > > clk to 52000000, rounded 52000000 [ 8.755345] sunxi-mmc 1c11000.mmc:
> > > setting clk to 52000000, rounded 52000000 [ 9.082510] sunxi-mmc
> > > 1c11000.mmc: setting clk to 52000000, rounded 52000000
> > >
> > > Here I tried to mount partition from eMMC...
> > >
> > > [ 72.167311] sunxi-mmc 1c11000.mmc: setting clk to 52000000, rounded
> > > 52000000 [ 72.269629] sunxi-mmc 1c11000.mmc: data error, sending stop
> > > command [ 73.268999] sunxi-mmc 1c11000.mmc: send stop command failed
> > > [/snip]
> > >
> > > And clock tree:
> > > [snip]
> > > pll-periph-base 3 3 0 1200000000 0
> > > 0 50000 pll-periph 6 6 0 600000000
> > > 0 0 50000 mmc2 3 3 0 50000000
> > > 0 0 50000 mmc2_sample 1 1 0
> > > 50000000 0 120 50000 mmc2_output 1 1 0
> > > 50000000 0 60 50000 ahb 18 18
> > > 0 300000000 0 0 50000 ahb-mmc2 1 1
> > > 0 300000000 0 0 50000 [/snip]
> > >
> > >
> > > And without patch:
> > > [snip]
> > > [ 2.003341] sunxi-mmc 1c11000.mmc: XXX: setting clk to 400000, rounded
> > > 400000 [ 2.019479] sunxi-mmc 1c11000.mmc: XXX: setting clk to 400000,
> > > rounded 400000 [ 2.039144] sunxi-mmc 1c11000.mmc: XXX: setting clk to
> > > 400000, rounded 400000 [ 2.047129] sunxi-mmc 1c11000.mmc: XXX: setting
> > > clk to 400000, rounded 400000 [ 2.054324] sunxi-mmc 1c11000.mmc: XXX:
> > > setting clk to 400000, rounded 400000 [ 2.064481] sunxi-mmc 1c11000.mmc:
> > > XXX: setting clk to 400000, rounded 400000 [ 2.091624] sunxi-mmc
> > > 1c11000.mmc: XXX: setting clk to 400000, rounded 400000 [ 2.168067]
> > > sunxi-mmc 1c11000.mmc: XXX: setting clk to 400000, rounded 400000 [
> > > 2.188239] sunxi-mmc 1c11000.mmc: XXX: setting clk to 52000000, rounded
> > > 51200000 [ 2.202779] sunxi-mmc 1c11000.mmc: XXX: setting clk to
> > > 52000000, rounded 51200000 [ 2.210817] sunxi-mmc 1c11000.mmc: XXX:
> > > setting clk to 52000000, rounded 51200000 [ 5.103358] sunxi-mmc
> > > 1c11000.mmc: XXX: setting clk to 52000000, rounded 51200000 [ 8.950237]
> > > sunxi-mmc 1c11000.mmc: XXX: setting clk to 52000000, rounded 51200000 [
> > > 9.376201] sunxi-mmc 1c11000.mmc: XXX: setting clk to 52000000, rounded
> > > 51200000 [ 113.618387] sunxi-mmc 1c11000.mmc: XXX: setting clk to
> > > 52000000, rounded 51200000 [ 113.707979] EXT4-fs (mmcblk1p4): recovery
> > > complete
> > > [ 113.728162] EXT4-fs (mmcblk1p4): mounted filesystem with ordered data
> > > mode. Opts: (null) [/snip]
> > >
> > > And clock tree:
> > > [snip]
> > > pll-ddr-base 2 2 0 768000000 0
> > > 0 50000 pll-ddr-other 1 1 0 768000000
> > > 0 0 50000 mmc2 0 0 0 51200000
> > > 0 0 50000 mmc2_sample 0 0 0
> > > 51200000 0 120 50000 mmc2_output 0 0 0
> > > 51200000 0 72 50000 [/snip]
> > >
> >
> > It seems to me that clock rate is set properly. It's even better than before
> > since there is no error between wanted and real clock. I bet that if you call
> > clk_get_rate() directly behind clk_set_rate() in mmc driver, you'll get
> > correct value.
> >
> > However, it seems that at some point some other peripheral changes it's parent
> > clock rate, which inadvertely changes emmc2 clock rate too. The only possible
> > clock which could interfere is sata. Can you disable driver in you kernel
> > config and try again?
>
> OK, tried following things in succession, but SATA disabling does not work:
>
> a) Marked all ahci stuff in devicetree as disabled
> b) Disable CONFIG_AHCI_SUNXI in kernel
> c) Even disabled SATA stuff in u-boot
But it works, when I allow mmc2 clock to set parent rate:
pll-periph-base 3 3 0 312000000 0 0 50000
mbus 1 1 0 78000000 0 0 50000
pll-periph-sata 1 1 0 26000000 0 0 50000
sata 1 1 0 26000000 0 0 50000
pll-periph 5 5 0 156000000 0 0 50000
mmc2 0 0 0 52000000 0 0 50000
mmc2_sample 0 0 0 52000000 0 120 50000
mmc2_output 0 0 0 52000000 0 120 50000
mmc0 0 0 0 39000000 0 0 50000
mmc0_sample 0 0 0 39000000 0 90 50000
mmc0_output 0 0 0 39000000 0 90 50000
Now, what I don't understand is why the `enable count` does not increase :(
---
diff --git a/drivers/clk/sunxi-ng/ccu-sun4i-a10.c b/drivers/clk/sunxi-ng/ccu-sun4i-a10.c
index 129ebd2588fd..605e13b4ef90 100644
--- a/drivers/clk/sunxi-ng/ccu-sun4i-a10.c
+++ b/drivers/clk/sunxi-ng/ccu-sun4i-a10.c
@@ -498,7 +498,7 @@ static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090,
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
- 0);
+ CLK_SET_RATE_PARENT);
/* MMC output and sample clocks are not present on A10 */
static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2_output", "mmc2",
>
> >
> > Best regards,
> > Jernej
>
> --
> You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
> To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe@googlegroups.com.
> For more options, visit https://groups.google.com/d/optout.
WARNING: multiple messages have this Message-ID (diff)
From: Priit Laes <plaes-q/aMd4JkU83YtjvyW6yDsg@public.gmane.org>
To: "Jernej Škrabec" <jernej.skrabec-gGgVlfcn5nU@public.gmane.org>
Cc: maxime.ripard-LDxbnhwyfcJBDgjK7y7TUQ@public.gmane.org,
wens-jdAy2FN1RRM@public.gmane.org,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org,
mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org,
sboyd-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org,
airlied-cv59FeDIM0c@public.gmane.org,
architt-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org,
a.hajda-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org,
Laurent.pinchart-ryLnwIuWjnjg/C1BVhZhaw@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org
Subject: Re: [PATCH v3 02/28] clk: sunxi-ng: Adjust MP clock parent rate when allowed
Date: Mon, 21 Jan 2019 13:34:33 +0000 [thread overview]
Message-ID: <20190121133433.lryqz7ivrj5cxu3g@plaes.org> (raw)
In-Reply-To: <20190121083729.7qsmj7drxvmnjoye-q/aMd4JkU83YtjvyW6yDsg@public.gmane.org>
On Mon, Jan 21, 2019 at 08:37:29AM +0000, Priit Laes wrote:
> On Fri, Jan 18, 2019 at 10:51:10PM +0100, Jernej Škrabec wrote:
> > Dne četrtek, 17. januar 2019 ob 08:24:02 CET je Priit Laes napisal(a):
> > > On Wed, Jan 16, 2019 at 06:00:32PM +0100, Jernej Škrabec wrote:
> > > > Dne sreda, 16. januar 2019 ob 13:09:58 CET je Priit Laes napisal(a):
> > > > > On Thu, Jan 10, 2019 at 06:10:59PM +0100, Jernej Škrabec wrote:
> > > > > > Dne četrtek, 10. januar 2019 ob 10:15:48 CET je Priit Laes napisal(a):
> > > > > > > On Sun, Nov 04, 2018 at 07:26:39PM +0100, Jernej Skrabec wrote:
> > > > > > > > Currently MP clocks don't consider adjusting parent rate even if
> > > > > > > > they
> > > > > > > > are allowed to do so. Such behaviour considerably lowers amount of
> > > > > > > > possible rates, which is very inconvenient when such clock is used
> > > > > > > > for
> > > > > > > > pixel clock, for example.
> > > > > > > >
> > > > > > > > In order to improve the situation, adjusting parent rate is
> > > > > > > > considered
> > > > > > > > when allowed.
> > > > > > > >
> > > > > > > > This code is inspired by clk_divider_bestdiv() function, which
> > > > > > > > does
> > > > > > > > basically the same thing for different clock type.
> > > > > > >
> > > > > > > This patch seems to break the eMMC support on Olinuxino-Lime2-eMMC
> > > > > > > boards:
> > > > > > >
> > > > > > > EXT4-fs (mmcblk1p4): INFO: recovery required on readonly filesystem
> > > > > > > EXT4-fs (mmcblk1p4): write access will be enabled during recovery
> > > > > > > sunxi-mmc 1c11000.mmc: data error, sending stop command
> > > > > > > sunxi-mmc 1c11000.mmc: send stop command failed
> > > > > >
> > > > > > I'm not familiar with A20. What is interesting is that emmc clocks
> > > > > > don't
> > > > > > have CLK_SET_RATE_PARENT flag set, so you shouldn't see any
> > > > > > difference.
> > > > > >
> > > > > > Can you post content of clk_summary with and without this patch?
> > > > >
> > > > > In both cases I booted from FEL with rootfs on sdcard and tried to mount
> > > > > partition from eMMC to /mnt. With your patch, last step it fails.
> > > > >
> > > > > pre-patch working:
> > > > > pll-ddr-other[768MHz] -> mmc2[512MHz]. (For some reason ahb-mmc2 is
> > > > > off?)
> > > > >
> > > > > post-patch not working:
> > > > > pll-periph[600MHz] -> mmc2[500Mhz], (ahb-mmc2 is enabled)
> > > > >
> > > > > Also, attached the logs.
> > > >
> > > > Thanks. Just one more request. Can you enable debug messages in mmc
> > > > driver?
> > > > I'm interested in output of this line:
> > > >
> > > > dev_dbg(mmc_dev(mmc), "setting clk to %d, rounded %ld\n",
> > > >
> > > > clock, rate);
> > >
> > > 1c11000 is eMMC:
> > > [snip]
> > > [ 1.961644] sunxi-mmc 1c11000.mmc: setting clk to 400000, rounded 400000
> > > [ 2.004091] sunxi-mmc 1c11000.mmc: setting clk to 400000, rounded 400000
> > > [ 2.020296] sunxi-mmc 1c11000.mmc: setting clk to 400000, rounded 400000
> > > [ 2.039917] sunxi-mmc 1c11000.mmc: setting clk to 400000, rounded 400000
> > > [ 2.047847] sunxi-mmc 1c11000.mmc: setting clk to 400000, rounded 400000
> > > [ 2.055053] sunxi-mmc 1c11000.mmc: setting clk to 400000, rounded 400000
> > > [ 2.065256] sunxi-mmc 1c11000.mmc: setting clk to 400000, rounded 400000
> > > [ 2.092351] sunxi-mmc 1c11000.mmc: setting clk to 400000, rounded 400000
> > > [ 2.168725] sunxi-mmc 1c11000.mmc: setting clk to 400000, rounded 400000
> > > [ 2.189403] sunxi-mmc 1c11000.mmc: setting clk to 52000000, rounded
> > > 52000000 [ 2.203340] sunxi-mmc 1c11000.mmc: setting clk to 52000000,
> > > rounded 52000000 [ 2.211412] sunxi-mmc 1c11000.mmc: setting clk to
> > > 52000000, rounded 52000000 [ 4.967865] sunxi-mmc 1c11000.mmc: setting
> > > clk to 52000000, rounded 52000000 [ 8.755345] sunxi-mmc 1c11000.mmc:
> > > setting clk to 52000000, rounded 52000000 [ 9.082510] sunxi-mmc
> > > 1c11000.mmc: setting clk to 52000000, rounded 52000000
> > >
> > > Here I tried to mount partition from eMMC...
> > >
> > > [ 72.167311] sunxi-mmc 1c11000.mmc: setting clk to 52000000, rounded
> > > 52000000 [ 72.269629] sunxi-mmc 1c11000.mmc: data error, sending stop
> > > command [ 73.268999] sunxi-mmc 1c11000.mmc: send stop command failed
> > > [/snip]
> > >
> > > And clock tree:
> > > [snip]
> > > pll-periph-base 3 3 0 1200000000 0
> > > 0 50000 pll-periph 6 6 0 600000000
> > > 0 0 50000 mmc2 3 3 0 50000000
> > > 0 0 50000 mmc2_sample 1 1 0
> > > 50000000 0 120 50000 mmc2_output 1 1 0
> > > 50000000 0 60 50000 ahb 18 18
> > > 0 300000000 0 0 50000 ahb-mmc2 1 1
> > > 0 300000000 0 0 50000 [/snip]
> > >
> > >
> > > And without patch:
> > > [snip]
> > > [ 2.003341] sunxi-mmc 1c11000.mmc: XXX: setting clk to 400000, rounded
> > > 400000 [ 2.019479] sunxi-mmc 1c11000.mmc: XXX: setting clk to 400000,
> > > rounded 400000 [ 2.039144] sunxi-mmc 1c11000.mmc: XXX: setting clk to
> > > 400000, rounded 400000 [ 2.047129] sunxi-mmc 1c11000.mmc: XXX: setting
> > > clk to 400000, rounded 400000 [ 2.054324] sunxi-mmc 1c11000.mmc: XXX:
> > > setting clk to 400000, rounded 400000 [ 2.064481] sunxi-mmc 1c11000.mmc:
> > > XXX: setting clk to 400000, rounded 400000 [ 2.091624] sunxi-mmc
> > > 1c11000.mmc: XXX: setting clk to 400000, rounded 400000 [ 2.168067]
> > > sunxi-mmc 1c11000.mmc: XXX: setting clk to 400000, rounded 400000 [
> > > 2.188239] sunxi-mmc 1c11000.mmc: XXX: setting clk to 52000000, rounded
> > > 51200000 [ 2.202779] sunxi-mmc 1c11000.mmc: XXX: setting clk to
> > > 52000000, rounded 51200000 [ 2.210817] sunxi-mmc 1c11000.mmc: XXX:
> > > setting clk to 52000000, rounded 51200000 [ 5.103358] sunxi-mmc
> > > 1c11000.mmc: XXX: setting clk to 52000000, rounded 51200000 [ 8.950237]
> > > sunxi-mmc 1c11000.mmc: XXX: setting clk to 52000000, rounded 51200000 [
> > > 9.376201] sunxi-mmc 1c11000.mmc: XXX: setting clk to 52000000, rounded
> > > 51200000 [ 113.618387] sunxi-mmc 1c11000.mmc: XXX: setting clk to
> > > 52000000, rounded 51200000 [ 113.707979] EXT4-fs (mmcblk1p4): recovery
> > > complete
> > > [ 113.728162] EXT4-fs (mmcblk1p4): mounted filesystem with ordered data
> > > mode. Opts: (null) [/snip]
> > >
> > > And clock tree:
> > > [snip]
> > > pll-ddr-base 2 2 0 768000000 0
> > > 0 50000 pll-ddr-other 1 1 0 768000000
> > > 0 0 50000 mmc2 0 0 0 51200000
> > > 0 0 50000 mmc2_sample 0 0 0
> > > 51200000 0 120 50000 mmc2_output 0 0 0
> > > 51200000 0 72 50000 [/snip]
> > >
> >
> > It seems to me that clock rate is set properly. It's even better than before
> > since there is no error between wanted and real clock. I bet that if you call
> > clk_get_rate() directly behind clk_set_rate() in mmc driver, you'll get
> > correct value.
> >
> > However, it seems that at some point some other peripheral changes it's parent
> > clock rate, which inadvertely changes emmc2 clock rate too. The only possible
> > clock which could interfere is sata. Can you disable driver in you kernel
> > config and try again?
>
> OK, tried following things in succession, but SATA disabling does not work:
>
> a) Marked all ahci stuff in devicetree as disabled
> b) Disable CONFIG_AHCI_SUNXI in kernel
> c) Even disabled SATA stuff in u-boot
But it works, when I allow mmc2 clock to set parent rate:
pll-periph-base 3 3 0 312000000 0 0 50000
mbus 1 1 0 78000000 0 0 50000
pll-periph-sata 1 1 0 26000000 0 0 50000
sata 1 1 0 26000000 0 0 50000
pll-periph 5 5 0 156000000 0 0 50000
mmc2 0 0 0 52000000 0 0 50000
mmc2_sample 0 0 0 52000000 0 120 50000
mmc2_output 0 0 0 52000000 0 120 50000
mmc0 0 0 0 39000000 0 0 50000
mmc0_sample 0 0 0 39000000 0 90 50000
mmc0_output 0 0 0 39000000 0 90 50000
Now, what I don't understand is why the `enable count` does not increase :(
---
diff --git a/drivers/clk/sunxi-ng/ccu-sun4i-a10.c b/drivers/clk/sunxi-ng/ccu-sun4i-a10.c
index 129ebd2588fd..605e13b4ef90 100644
--- a/drivers/clk/sunxi-ng/ccu-sun4i-a10.c
+++ b/drivers/clk/sunxi-ng/ccu-sun4i-a10.c
@@ -498,7 +498,7 @@ static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090,
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
- 0);
+ CLK_SET_RATE_PARENT);
/* MMC output and sample clocks are not present on A10 */
static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2_output", "mmc2",
>
> >
> > Best regards,
> > Jernej
>
> --
> You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
> To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe-/JYPxA39Uh5TLH3MbocFF+G/Ez6ZCGd0@public.gmane.org
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WARNING: multiple messages have this Message-ID (diff)
From: Priit Laes <plaes@plaes.org>
To: "Jernej Škrabec" <jernej.skrabec@siol.net>
Cc: linux-arm-kernel@lists.infradead.org, airlied@linux.ie,
architt@codeaurora.org, a.hajda@samsung.com,
maxime.ripard@bootlin.com, mturquette@baylibre.com,
linux-sunxi@googlegroups.com, linux-kernel@vger.kernel.org,
dri-devel@lists.freedesktop.org, sboyd@kernel.org, wens@csie.org,
robh+dt@kernel.org, Laurent.pinchart@ideasonboard.com,
linux-clk@vger.kernel.org, devicetree@vger.kernel.org
Subject: Re: [linux-sunxi] [PATCH v3 02/28] clk: sunxi-ng: Adjust MP clock parent rate when allowed
Date: Mon, 21 Jan 2019 13:34:33 +0000 [thread overview]
Message-ID: <20190121133433.lryqz7ivrj5cxu3g@plaes.org> (raw)
In-Reply-To: <20190121083729.7qsmj7drxvmnjoye@plaes.org>
On Mon, Jan 21, 2019 at 08:37:29AM +0000, Priit Laes wrote:
> On Fri, Jan 18, 2019 at 10:51:10PM +0100, Jernej Škrabec wrote:
> > Dne četrtek, 17. januar 2019 ob 08:24:02 CET je Priit Laes napisal(a):
> > > On Wed, Jan 16, 2019 at 06:00:32PM +0100, Jernej Škrabec wrote:
> > > > Dne sreda, 16. januar 2019 ob 13:09:58 CET je Priit Laes napisal(a):
> > > > > On Thu, Jan 10, 2019 at 06:10:59PM +0100, Jernej Škrabec wrote:
> > > > > > Dne četrtek, 10. januar 2019 ob 10:15:48 CET je Priit Laes napisal(a):
> > > > > > > On Sun, Nov 04, 2018 at 07:26:39PM +0100, Jernej Skrabec wrote:
> > > > > > > > Currently MP clocks don't consider adjusting parent rate even if
> > > > > > > > they
> > > > > > > > are allowed to do so. Such behaviour considerably lowers amount of
> > > > > > > > possible rates, which is very inconvenient when such clock is used
> > > > > > > > for
> > > > > > > > pixel clock, for example.
> > > > > > > >
> > > > > > > > In order to improve the situation, adjusting parent rate is
> > > > > > > > considered
> > > > > > > > when allowed.
> > > > > > > >
> > > > > > > > This code is inspired by clk_divider_bestdiv() function, which
> > > > > > > > does
> > > > > > > > basically the same thing for different clock type.
> > > > > > >
> > > > > > > This patch seems to break the eMMC support on Olinuxino-Lime2-eMMC
> > > > > > > boards:
> > > > > > >
> > > > > > > EXT4-fs (mmcblk1p4): INFO: recovery required on readonly filesystem
> > > > > > > EXT4-fs (mmcblk1p4): write access will be enabled during recovery
> > > > > > > sunxi-mmc 1c11000.mmc: data error, sending stop command
> > > > > > > sunxi-mmc 1c11000.mmc: send stop command failed
> > > > > >
> > > > > > I'm not familiar with A20. What is interesting is that emmc clocks
> > > > > > don't
> > > > > > have CLK_SET_RATE_PARENT flag set, so you shouldn't see any
> > > > > > difference.
> > > > > >
> > > > > > Can you post content of clk_summary with and without this patch?
> > > > >
> > > > > In both cases I booted from FEL with rootfs on sdcard and tried to mount
> > > > > partition from eMMC to /mnt. With your patch, last step it fails.
> > > > >
> > > > > pre-patch working:
> > > > > pll-ddr-other[768MHz] -> mmc2[512MHz]. (For some reason ahb-mmc2 is
> > > > > off?)
> > > > >
> > > > > post-patch not working:
> > > > > pll-periph[600MHz] -> mmc2[500Mhz], (ahb-mmc2 is enabled)
> > > > >
> > > > > Also, attached the logs.
> > > >
> > > > Thanks. Just one more request. Can you enable debug messages in mmc
> > > > driver?
> > > > I'm interested in output of this line:
> > > >
> > > > dev_dbg(mmc_dev(mmc), "setting clk to %d, rounded %ld\n",
> > > >
> > > > clock, rate);
> > >
> > > 1c11000 is eMMC:
> > > [snip]
> > > [ 1.961644] sunxi-mmc 1c11000.mmc: setting clk to 400000, rounded 400000
> > > [ 2.004091] sunxi-mmc 1c11000.mmc: setting clk to 400000, rounded 400000
> > > [ 2.020296] sunxi-mmc 1c11000.mmc: setting clk to 400000, rounded 400000
> > > [ 2.039917] sunxi-mmc 1c11000.mmc: setting clk to 400000, rounded 400000
> > > [ 2.047847] sunxi-mmc 1c11000.mmc: setting clk to 400000, rounded 400000
> > > [ 2.055053] sunxi-mmc 1c11000.mmc: setting clk to 400000, rounded 400000
> > > [ 2.065256] sunxi-mmc 1c11000.mmc: setting clk to 400000, rounded 400000
> > > [ 2.092351] sunxi-mmc 1c11000.mmc: setting clk to 400000, rounded 400000
> > > [ 2.168725] sunxi-mmc 1c11000.mmc: setting clk to 400000, rounded 400000
> > > [ 2.189403] sunxi-mmc 1c11000.mmc: setting clk to 52000000, rounded
> > > 52000000 [ 2.203340] sunxi-mmc 1c11000.mmc: setting clk to 52000000,
> > > rounded 52000000 [ 2.211412] sunxi-mmc 1c11000.mmc: setting clk to
> > > 52000000, rounded 52000000 [ 4.967865] sunxi-mmc 1c11000.mmc: setting
> > > clk to 52000000, rounded 52000000 [ 8.755345] sunxi-mmc 1c11000.mmc:
> > > setting clk to 52000000, rounded 52000000 [ 9.082510] sunxi-mmc
> > > 1c11000.mmc: setting clk to 52000000, rounded 52000000
> > >
> > > Here I tried to mount partition from eMMC...
> > >
> > > [ 72.167311] sunxi-mmc 1c11000.mmc: setting clk to 52000000, rounded
> > > 52000000 [ 72.269629] sunxi-mmc 1c11000.mmc: data error, sending stop
> > > command [ 73.268999] sunxi-mmc 1c11000.mmc: send stop command failed
> > > [/snip]
> > >
> > > And clock tree:
> > > [snip]
> > > pll-periph-base 3 3 0 1200000000 0
> > > 0 50000 pll-periph 6 6 0 600000000
> > > 0 0 50000 mmc2 3 3 0 50000000
> > > 0 0 50000 mmc2_sample 1 1 0
> > > 50000000 0 120 50000 mmc2_output 1 1 0
> > > 50000000 0 60 50000 ahb 18 18
> > > 0 300000000 0 0 50000 ahb-mmc2 1 1
> > > 0 300000000 0 0 50000 [/snip]
> > >
> > >
> > > And without patch:
> > > [snip]
> > > [ 2.003341] sunxi-mmc 1c11000.mmc: XXX: setting clk to 400000, rounded
> > > 400000 [ 2.019479] sunxi-mmc 1c11000.mmc: XXX: setting clk to 400000,
> > > rounded 400000 [ 2.039144] sunxi-mmc 1c11000.mmc: XXX: setting clk to
> > > 400000, rounded 400000 [ 2.047129] sunxi-mmc 1c11000.mmc: XXX: setting
> > > clk to 400000, rounded 400000 [ 2.054324] sunxi-mmc 1c11000.mmc: XXX:
> > > setting clk to 400000, rounded 400000 [ 2.064481] sunxi-mmc 1c11000.mmc:
> > > XXX: setting clk to 400000, rounded 400000 [ 2.091624] sunxi-mmc
> > > 1c11000.mmc: XXX: setting clk to 400000, rounded 400000 [ 2.168067]
> > > sunxi-mmc 1c11000.mmc: XXX: setting clk to 400000, rounded 400000 [
> > > 2.188239] sunxi-mmc 1c11000.mmc: XXX: setting clk to 52000000, rounded
> > > 51200000 [ 2.202779] sunxi-mmc 1c11000.mmc: XXX: setting clk to
> > > 52000000, rounded 51200000 [ 2.210817] sunxi-mmc 1c11000.mmc: XXX:
> > > setting clk to 52000000, rounded 51200000 [ 5.103358] sunxi-mmc
> > > 1c11000.mmc: XXX: setting clk to 52000000, rounded 51200000 [ 8.950237]
> > > sunxi-mmc 1c11000.mmc: XXX: setting clk to 52000000, rounded 51200000 [
> > > 9.376201] sunxi-mmc 1c11000.mmc: XXX: setting clk to 52000000, rounded
> > > 51200000 [ 113.618387] sunxi-mmc 1c11000.mmc: XXX: setting clk to
> > > 52000000, rounded 51200000 [ 113.707979] EXT4-fs (mmcblk1p4): recovery
> > > complete
> > > [ 113.728162] EXT4-fs (mmcblk1p4): mounted filesystem with ordered data
> > > mode. Opts: (null) [/snip]
> > >
> > > And clock tree:
> > > [snip]
> > > pll-ddr-base 2 2 0 768000000 0
> > > 0 50000 pll-ddr-other 1 1 0 768000000
> > > 0 0 50000 mmc2 0 0 0 51200000
> > > 0 0 50000 mmc2_sample 0 0 0
> > > 51200000 0 120 50000 mmc2_output 0 0 0
> > > 51200000 0 72 50000 [/snip]
> > >
> >
> > It seems to me that clock rate is set properly. It's even better than before
> > since there is no error between wanted and real clock. I bet that if you call
> > clk_get_rate() directly behind clk_set_rate() in mmc driver, you'll get
> > correct value.
> >
> > However, it seems that at some point some other peripheral changes it's parent
> > clock rate, which inadvertely changes emmc2 clock rate too. The only possible
> > clock which could interfere is sata. Can you disable driver in you kernel
> > config and try again?
>
> OK, tried following things in succession, but SATA disabling does not work:
>
> a) Marked all ahci stuff in devicetree as disabled
> b) Disable CONFIG_AHCI_SUNXI in kernel
> c) Even disabled SATA stuff in u-boot
But it works, when I allow mmc2 clock to set parent rate:
pll-periph-base 3 3 0 312000000 0 0 50000
mbus 1 1 0 78000000 0 0 50000
pll-periph-sata 1 1 0 26000000 0 0 50000
sata 1 1 0 26000000 0 0 50000
pll-periph 5 5 0 156000000 0 0 50000
mmc2 0 0 0 52000000 0 0 50000
mmc2_sample 0 0 0 52000000 0 120 50000
mmc2_output 0 0 0 52000000 0 120 50000
mmc0 0 0 0 39000000 0 0 50000
mmc0_sample 0 0 0 39000000 0 90 50000
mmc0_output 0 0 0 39000000 0 90 50000
Now, what I don't understand is why the `enable count` does not increase :(
---
diff --git a/drivers/clk/sunxi-ng/ccu-sun4i-a10.c b/drivers/clk/sunxi-ng/ccu-sun4i-a10.c
index 129ebd2588fd..605e13b4ef90 100644
--- a/drivers/clk/sunxi-ng/ccu-sun4i-a10.c
+++ b/drivers/clk/sunxi-ng/ccu-sun4i-a10.c
@@ -498,7 +498,7 @@ static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090,
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
- 0);
+ CLK_SET_RATE_PARENT);
/* MMC output and sample clocks are not present on A10 */
static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2_output", "mmc2",
>
> >
> > Best regards,
> > Jernej
>
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next prev parent reply other threads:[~2019-01-21 13:34 UTC|newest]
Thread overview: 126+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-11-04 18:26 [PATCH v3 00/28] Allwinner H6 DE3 and HDMI support Jernej Skrabec
2018-11-04 18:26 ` Jernej Skrabec
2018-11-04 18:26 ` Jernej Skrabec
2018-11-04 18:26 ` [PATCH v3 01/28] dt-bindings: bus: add H6 DE3 bus binding Jernej Skrabec
2018-11-04 18:26 ` Jernej Skrabec
2018-11-04 18:26 ` Jernej Skrabec
2018-11-04 18:26 ` [PATCH v3 02/28] clk: sunxi-ng: Adjust MP clock parent rate when allowed Jernej Skrabec
2018-11-04 18:26 ` Jernej Skrabec
2018-11-04 18:26 ` Jernej Skrabec
2019-01-10 9:15 ` [linux-sunxi] " Priit Laes
2019-01-10 9:15 ` Priit Laes
2019-01-10 17:10 ` Jernej Škrabec
2019-01-10 17:10 ` Jernej Škrabec
2019-01-10 17:10 ` Jernej Škrabec
2019-01-16 12:09 ` [linux-sunxi] " Priit Laes
2019-01-16 12:09 ` Priit Laes
2019-01-16 17:00 ` Jernej Škrabec
2019-01-16 17:00 ` Jernej Škrabec
2019-01-16 17:00 ` Jernej Škrabec
2019-01-17 7:24 ` [linux-sunxi] " Priit Laes
2019-01-17 7:24 ` Priit Laes
2019-01-17 7:24 ` Priit Laes
2019-01-18 21:51 ` [linux-sunxi] " Jernej Škrabec
2019-01-18 21:51 ` Jernej Škrabec
2019-01-18 21:51 ` Jernej Škrabec
2019-01-21 8:37 ` [linux-sunxi] " Priit Laes
2019-01-21 8:37 ` Priit Laes
2019-01-21 13:34 ` Priit Laes [this message]
2019-01-21 13:34 ` Priit Laes
2019-01-21 13:34 ` Priit Laes
2019-01-21 18:13 ` [linux-sunxi] " Jernej Škrabec
2019-01-21 18:13 ` Jernej Škrabec
2019-03-19 10:34 ` Priit Laes
2019-03-19 10:34 ` Priit Laes
2019-03-19 10:34 ` Priit Laes
2018-11-04 18:26 ` [PATCH v3 03/28] clk: sunxi-ng: Use u64 for calculation of NM rate Jernej Skrabec
2018-11-04 18:26 ` Jernej Skrabec
2018-11-04 18:26 ` Jernej Skrabec
2018-11-04 18:26 ` [PATCH v3 04/28] clk: sunxi-ng: h6: Set video PLLs limits Jernej Skrabec
2018-11-04 18:26 ` Jernej Skrabec
2018-11-04 18:26 ` Jernej Skrabec
2018-11-04 18:26 ` [PATCH v3 05/28] dt-bindings: clock: sun8i-de2: Add H6 DE3 clock description Jernej Skrabec
2018-11-04 18:26 ` Jernej Skrabec
2018-11-04 18:26 ` [PATCH v3 06/28] clk: sunxi-ng: Add support for H6 DE3 clocks Jernej Skrabec
2018-11-04 18:26 ` Jernej Skrabec
2018-11-04 18:26 ` Jernej Skrabec
2018-11-04 18:26 ` [PATCH v3 07/28] dt-bindings: display: sun4i-drm: Add H6 display engine compatibles Jernej Skrabec
2018-11-04 18:26 ` Jernej Skrabec
2018-11-04 18:26 ` Jernej Skrabec
2018-11-04 18:26 ` [PATCH v3 08/28] drm/sun4i: Add compatible for H6 display engine Jernej Skrabec
2018-11-04 18:26 ` Jernej Skrabec
2018-11-04 18:26 ` Jernej Skrabec
2018-11-04 18:26 ` [PATCH v3 09/28] drm/sun4i: Rework DE2 register defines Jernej Skrabec
2018-11-04 18:26 ` Jernej Skrabec
2018-11-04 18:26 ` Jernej Skrabec
2018-11-04 18:26 ` [PATCH v3 10/28] drm/sun4i: Fix DE2 mixer size Jernej Skrabec
2018-11-04 18:26 ` Jernej Skrabec
2018-11-04 18:26 ` Jernej Skrabec
2018-11-04 18:26 ` [PATCH v3 11/28] drm/sun4i: Disable unused DE2 sub-engines Jernej Skrabec
2018-11-04 18:26 ` Jernej Skrabec
2018-11-04 18:26 ` [PATCH v3 12/28] drm/sun4i: Add basic support for DE3 Jernej Skrabec
2018-11-04 18:26 ` Jernej Skrabec
2018-11-04 18:26 ` Jernej Skrabec
2018-11-04 18:26 ` [PATCH v3 13/28] drm/sun4i: Add support for H6 DE3 mixer 0 Jernej Skrabec
2018-11-04 18:26 ` Jernej Skrabec
2018-11-04 18:26 ` Jernej Skrabec
2018-11-04 18:26 ` [PATCH v3 14/28] drm/bridge/synopsys: dw-hdmi: Enable workaround for v2.12a Jernej Skrabec
2018-11-04 18:26 ` Jernej Skrabec
2018-11-04 18:26 ` Jernej Skrabec
2018-11-04 18:26 ` [PATCH v3 15/28] drm/sun4i: Not all DW HDMI controllers has scrambled addresses Jernej Skrabec
2018-11-04 18:26 ` Jernej Skrabec
2018-11-04 18:26 ` Jernej Skrabec
2018-11-04 18:26 ` [PATCH v3 16/28] drm/sun4i: dw-hdmi: Make mode_valid function configurable Jernej Skrabec
2018-11-04 18:26 ` Jernej Skrabec
2018-11-04 18:26 ` Jernej Skrabec
2018-11-04 18:26 ` [PATCH v3 17/28] drm/sun4i: dw-hdmi: Add quirk for setting TMDS clock Jernej Skrabec
2018-11-04 18:26 ` Jernej Skrabec
2018-11-04 18:26 ` Jernej Skrabec
2018-11-04 18:26 ` [PATCH v3 18/28] dt-bindings: display: sunxi: add DT binding for Allwinner H6 DW HDMI Jernej Skrabec
2018-11-04 18:26 ` Jernej Skrabec
2018-11-04 18:26 ` [PATCH v3 19/28] drm/sun4i: Add support for H6 DW HDMI controller Jernej Skrabec
2018-11-04 18:26 ` Jernej Skrabec
2018-11-04 18:26 ` [PATCH v3 20/28] drm/sun4i: dw-hdmi-phy: Reorder quirks by family Jernej Skrabec
2018-11-04 18:26 ` Jernej Skrabec
2018-11-04 18:26 ` Jernej Skrabec
2018-11-04 18:26 ` [PATCH v3 21/28] drm/sun4i: Add support for Synopsys HDMI PHY Jernej Skrabec
2018-11-04 18:26 ` Jernej Skrabec
2018-11-04 18:26 ` Jernej Skrabec
2018-11-04 18:26 ` [PATCH v3 22/28] drm/sun4i: Add support for H6 " Jernej Skrabec
2018-11-04 18:26 ` Jernej Skrabec
2018-11-04 18:26 ` Jernej Skrabec
2018-11-04 18:27 ` [PATCH v3 23/28] drm/sun4i: Initialize registers in tcon-top driver Jernej Skrabec
2018-11-04 18:27 ` Jernej Skrabec
2018-11-04 18:27 ` Jernej Skrabec
2018-11-04 18:27 ` [PATCH v3 24/28] drm: sun4i: add quirks for TCON TOP Jernej Skrabec
2018-11-04 18:27 ` Jernej Skrabec
2018-11-04 18:27 ` Jernej Skrabec
2018-11-04 18:27 ` [PATCH v3 25/28] dt-bindings: display: sun4i-drm: document H6 " Jernej Skrabec
2018-11-04 18:27 ` Jernej Skrabec
2018-11-04 18:27 ` Jernej Skrabec
2018-11-04 18:27 ` [PATCH v3 26/28] drm: sun4i: add support for " Jernej Skrabec
2018-11-04 18:27 ` Jernej Skrabec
2018-11-04 18:27 ` Jernej Skrabec
2018-11-04 18:27 ` [PATCH v3 27/28] arm64: dts: allwinner: h6: Add HDMI pipeline Jernej Skrabec
2018-11-04 18:27 ` Jernej Skrabec
2018-11-04 18:27 ` Jernej Skrabec
2018-11-04 18:27 ` [PATCH v3 28/28] arm64: dts: allwinner: h6: Enable HDMI output on Pine H64 board Jernej Skrabec
2018-11-04 18:27 ` Jernej Skrabec
2018-11-04 18:27 ` Jernej Skrabec
2018-11-05 9:43 ` [PATCH v3 00/28] Allwinner H6 DE3 and HDMI support Maxime Ripard
2018-11-05 9:43 ` Maxime Ripard
2018-11-06 15:54 ` Jernej Škrabec
2018-11-06 15:54 ` Jernej Škrabec
2018-11-06 15:54 ` Jernej Škrabec
2018-11-06 17:20 ` Jernej Škrabec
2018-11-06 17:20 ` Jernej Škrabec
2018-11-06 17:20 ` Jernej Škrabec
2018-11-07 9:44 ` Maxime Ripard
2018-11-07 9:44 ` Maxime Ripard
2018-11-07 9:44 ` Maxime Ripard
2018-12-03 18:09 ` Jernej Škrabec
2018-12-03 18:09 ` Jernej Škrabec
2018-12-03 18:09 ` Jernej Škrabec
2018-12-04 8:29 ` Maxime Ripard
2018-12-04 8:29 ` Maxime Ripard
2018-12-04 8:29 ` Maxime Ripard
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