From: Boris Brezillon <bbrezillon@kernel.org>
To: <Tudor.Ambarus@microchip.com>
Cc: <broonie@kernel.org>, <robh+dt@kernel.org>,
<mark.rutland@arm.com>, <Nicolas.Ferre@microchip.com>,
<alexandre.belloni@bootlin.com>,
<Ludovic.Desroches@microchip.com>,
<Cyrille.Pitchen@microchip.com>, <bugalski.piotr@gmail.com>,
<linux-spi@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <linux-mtd@lists.infradead.org>
Subject: Re: [PATCH v4 01/13] spi: atmel-quadspi: cache MR value to avoid a write access
Date: Mon, 4 Feb 2019 15:00:05 +0100 [thread overview]
Message-ID: <20190204150005.3567bf29@bbrezillon> (raw)
In-Reply-To: <20190204100910.26701-2-tudor.ambarus@microchip.com>
On Mon, 4 Feb 2019 10:09:22 +0000
<Tudor.Ambarus@microchip.com> wrote:
> From: Tudor Ambarus <tudor.ambarus@microchip.com>
>
> Set the controller by default in Serial Memory Mode (SMM) at probe.
> Cache Mode Register (MR) value to avoid write access when setting
> the controller in serial memory mode at exec_op().
>
> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Boris Brezillon <bbrezillon@kernel.org>
> ---
> v4: s/smm/mr, init controller in serial memory mode by default
> v3: update smm value when different. rename mr/smm
> v2: cache MR value instead of moving the write access at probe
>
> drivers/spi/atmel-quadspi.c | 14 +++++++++++++-
> 1 file changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/spi/atmel-quadspi.c b/drivers/spi/atmel-quadspi.c
> index ddc712410812..d6864d29f294 100644
> --- a/drivers/spi/atmel-quadspi.c
> +++ b/drivers/spi/atmel-quadspi.c
> @@ -155,6 +155,7 @@ struct atmel_qspi {
> struct clk *clk;
> struct platform_device *pdev;
> u32 pending;
> + u32 mr;
> struct completion cmd_completion;
> };
>
> @@ -238,7 +239,14 @@ static int atmel_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
> icr = QSPI_ICR_INST(op->cmd.opcode);
> ifr = QSPI_IFR_INSTEN;
>
> - qspi_writel(aq, QSPI_MR, QSPI_MR_SMM);
> + /*
> + * If the QSPI controller is set in regular SPI mode, set it in
> + * Serial Memory Mode (SMM).
> + */
> + if (aq->mr != QSPI_MR_SMM) {
> + qspi_writel(aq, QSPI_MR, QSPI_MR_SMM);
> + aq->mr = QSPI_MR_SMM;
> + }
>
> mode = find_mode(op);
> if (mode < 0)
> @@ -381,6 +389,10 @@ static int atmel_qspi_init(struct atmel_qspi *aq)
> /* Reset the QSPI controller */
> qspi_writel(aq, QSPI_CR, QSPI_CR_SWRST);
>
> + /* Set the QSPI controller by default in Serial Memory Mode */
> + qspi_writel(aq, QSPI_MR, QSPI_MR_SMM);
> + aq->mr = QSPI_MR_SMM;
> +
> /* Enable the QSPI controller */
> qspi_writel(aq, QSPI_CR, QSPI_CR_QSPIEN);
>
WARNING: multiple messages have this Message-ID (diff)
From: Boris Brezillon <bbrezillon@kernel.org>
To: Tudor.Ambarus@microchip.com
Cc: broonie@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com,
Nicolas.Ferre@microchip.com, alexandre.belloni@bootlin.com,
Ludovic.Desroches@microchip.com, Cyrille.Pitchen@microchip.com,
bugalski.piotr@gmail.com, linux-spi@vger.kernel.org,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org
Subject: Re: [PATCH v4 01/13] spi: atmel-quadspi: cache MR value to avoid a write access
Date: Mon, 4 Feb 2019 15:00:05 +0100 [thread overview]
Message-ID: <20190204150005.3567bf29@bbrezillon> (raw)
In-Reply-To: <20190204100910.26701-2-tudor.ambarus@microchip.com>
On Mon, 4 Feb 2019 10:09:22 +0000
<Tudor.Ambarus@microchip.com> wrote:
> From: Tudor Ambarus <tudor.ambarus@microchip.com>
>
> Set the controller by default in Serial Memory Mode (SMM) at probe.
> Cache Mode Register (MR) value to avoid write access when setting
> the controller in serial memory mode at exec_op().
>
> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Boris Brezillon <bbrezillon@kernel.org>
> ---
> v4: s/smm/mr, init controller in serial memory mode by default
> v3: update smm value when different. rename mr/smm
> v2: cache MR value instead of moving the write access at probe
>
> drivers/spi/atmel-quadspi.c | 14 +++++++++++++-
> 1 file changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/spi/atmel-quadspi.c b/drivers/spi/atmel-quadspi.c
> index ddc712410812..d6864d29f294 100644
> --- a/drivers/spi/atmel-quadspi.c
> +++ b/drivers/spi/atmel-quadspi.c
> @@ -155,6 +155,7 @@ struct atmel_qspi {
> struct clk *clk;
> struct platform_device *pdev;
> u32 pending;
> + u32 mr;
> struct completion cmd_completion;
> };
>
> @@ -238,7 +239,14 @@ static int atmel_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
> icr = QSPI_ICR_INST(op->cmd.opcode);
> ifr = QSPI_IFR_INSTEN;
>
> - qspi_writel(aq, QSPI_MR, QSPI_MR_SMM);
> + /*
> + * If the QSPI controller is set in regular SPI mode, set it in
> + * Serial Memory Mode (SMM).
> + */
> + if (aq->mr != QSPI_MR_SMM) {
> + qspi_writel(aq, QSPI_MR, QSPI_MR_SMM);
> + aq->mr = QSPI_MR_SMM;
> + }
>
> mode = find_mode(op);
> if (mode < 0)
> @@ -381,6 +389,10 @@ static int atmel_qspi_init(struct atmel_qspi *aq)
> /* Reset the QSPI controller */
> qspi_writel(aq, QSPI_CR, QSPI_CR_SWRST);
>
> + /* Set the QSPI controller by default in Serial Memory Mode */
> + qspi_writel(aq, QSPI_MR, QSPI_MR_SMM);
> + aq->mr = QSPI_MR_SMM;
> +
> /* Enable the QSPI controller */
> qspi_writel(aq, QSPI_CR, QSPI_CR_QSPIEN);
>
WARNING: multiple messages have this Message-ID (diff)
From: Boris Brezillon <bbrezillon@kernel.org>
To: <Tudor.Ambarus@microchip.com>
Cc: mark.rutland@arm.com, devicetree@vger.kernel.org,
alexandre.belloni@bootlin.com, linux-kernel@vger.kernel.org,
Cyrille.Pitchen@microchip.com, Nicolas.Ferre@microchip.com,
robh+dt@kernel.org, linux-spi@vger.kernel.org,
Ludovic.Desroches@microchip.com, broonie@kernel.org,
linux-mtd@lists.infradead.org, bugalski.piotr@gmail.com,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v4 01/13] spi: atmel-quadspi: cache MR value to avoid a write access
Date: Mon, 4 Feb 2019 15:00:05 +0100 [thread overview]
Message-ID: <20190204150005.3567bf29@bbrezillon> (raw)
In-Reply-To: <20190204100910.26701-2-tudor.ambarus@microchip.com>
On Mon, 4 Feb 2019 10:09:22 +0000
<Tudor.Ambarus@microchip.com> wrote:
> From: Tudor Ambarus <tudor.ambarus@microchip.com>
>
> Set the controller by default in Serial Memory Mode (SMM) at probe.
> Cache Mode Register (MR) value to avoid write access when setting
> the controller in serial memory mode at exec_op().
>
> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Boris Brezillon <bbrezillon@kernel.org>
> ---
> v4: s/smm/mr, init controller in serial memory mode by default
> v3: update smm value when different. rename mr/smm
> v2: cache MR value instead of moving the write access at probe
>
> drivers/spi/atmel-quadspi.c | 14 +++++++++++++-
> 1 file changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/spi/atmel-quadspi.c b/drivers/spi/atmel-quadspi.c
> index ddc712410812..d6864d29f294 100644
> --- a/drivers/spi/atmel-quadspi.c
> +++ b/drivers/spi/atmel-quadspi.c
> @@ -155,6 +155,7 @@ struct atmel_qspi {
> struct clk *clk;
> struct platform_device *pdev;
> u32 pending;
> + u32 mr;
> struct completion cmd_completion;
> };
>
> @@ -238,7 +239,14 @@ static int atmel_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
> icr = QSPI_ICR_INST(op->cmd.opcode);
> ifr = QSPI_IFR_INSTEN;
>
> - qspi_writel(aq, QSPI_MR, QSPI_MR_SMM);
> + /*
> + * If the QSPI controller is set in regular SPI mode, set it in
> + * Serial Memory Mode (SMM).
> + */
> + if (aq->mr != QSPI_MR_SMM) {
> + qspi_writel(aq, QSPI_MR, QSPI_MR_SMM);
> + aq->mr = QSPI_MR_SMM;
> + }
>
> mode = find_mode(op);
> if (mode < 0)
> @@ -381,6 +389,10 @@ static int atmel_qspi_init(struct atmel_qspi *aq)
> /* Reset the QSPI controller */
> qspi_writel(aq, QSPI_CR, QSPI_CR_SWRST);
>
> + /* Set the QSPI controller by default in Serial Memory Mode */
> + qspi_writel(aq, QSPI_MR, QSPI_MR_SMM);
> + aq->mr = QSPI_MR_SMM;
> +
> /* Enable the QSPI controller */
> qspi_writel(aq, QSPI_CR, QSPI_CR_QSPIEN);
>
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
WARNING: multiple messages have this Message-ID (diff)
From: Boris Brezillon <bbrezillon@kernel.org>
To: <Tudor.Ambarus@microchip.com>
Cc: mark.rutland@arm.com, devicetree@vger.kernel.org,
alexandre.belloni@bootlin.com, linux-kernel@vger.kernel.org,
Cyrille.Pitchen@microchip.com, robh+dt@kernel.org,
linux-spi@vger.kernel.org, Ludovic.Desroches@microchip.com,
broonie@kernel.org, linux-mtd@lists.infradead.org,
bugalski.piotr@gmail.com, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v4 01/13] spi: atmel-quadspi: cache MR value to avoid a write access
Date: Mon, 4 Feb 2019 15:00:05 +0100 [thread overview]
Message-ID: <20190204150005.3567bf29@bbrezillon> (raw)
In-Reply-To: <20190204100910.26701-2-tudor.ambarus@microchip.com>
On Mon, 4 Feb 2019 10:09:22 +0000
<Tudor.Ambarus@microchip.com> wrote:
> From: Tudor Ambarus <tudor.ambarus@microchip.com>
>
> Set the controller by default in Serial Memory Mode (SMM) at probe.
> Cache Mode Register (MR) value to avoid write access when setting
> the controller in serial memory mode at exec_op().
>
> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Boris Brezillon <bbrezillon@kernel.org>
> ---
> v4: s/smm/mr, init controller in serial memory mode by default
> v3: update smm value when different. rename mr/smm
> v2: cache MR value instead of moving the write access at probe
>
> drivers/spi/atmel-quadspi.c | 14 +++++++++++++-
> 1 file changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/spi/atmel-quadspi.c b/drivers/spi/atmel-quadspi.c
> index ddc712410812..d6864d29f294 100644
> --- a/drivers/spi/atmel-quadspi.c
> +++ b/drivers/spi/atmel-quadspi.c
> @@ -155,6 +155,7 @@ struct atmel_qspi {
> struct clk *clk;
> struct platform_device *pdev;
> u32 pending;
> + u32 mr;
> struct completion cmd_completion;
> };
>
> @@ -238,7 +239,14 @@ static int atmel_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
> icr = QSPI_ICR_INST(op->cmd.opcode);
> ifr = QSPI_IFR_INSTEN;
>
> - qspi_writel(aq, QSPI_MR, QSPI_MR_SMM);
> + /*
> + * If the QSPI controller is set in regular SPI mode, set it in
> + * Serial Memory Mode (SMM).
> + */
> + if (aq->mr != QSPI_MR_SMM) {
> + qspi_writel(aq, QSPI_MR, QSPI_MR_SMM);
> + aq->mr = QSPI_MR_SMM;
> + }
>
> mode = find_mode(op);
> if (mode < 0)
> @@ -381,6 +389,10 @@ static int atmel_qspi_init(struct atmel_qspi *aq)
> /* Reset the QSPI controller */
> qspi_writel(aq, QSPI_CR, QSPI_CR_SWRST);
>
> + /* Set the QSPI controller by default in Serial Memory Mode */
> + qspi_writel(aq, QSPI_MR, QSPI_MR_SMM);
> + aq->mr = QSPI_MR_SMM;
> +
> /* Enable the QSPI controller */
> qspi_writel(aq, QSPI_CR, QSPI_CR_QSPIEN);
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2019-02-04 14:00 UTC|newest]
Thread overview: 77+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-02-04 10:09 [PATCH v4 00/13] spi: atmel-quadspi: introduce sam9x60 qspi controller Tudor.Ambarus
2019-02-04 10:09 ` Tudor.Ambarus
2019-02-04 10:09 ` Tudor.Ambarus
2019-02-04 10:09 ` Tudor.Ambarus
2019-02-04 10:09 ` [PATCH v4 01/13] spi: atmel-quadspi: cache MR value to avoid a write access Tudor.Ambarus
2019-02-04 10:09 ` Tudor.Ambarus
2019-02-04 10:09 ` Tudor.Ambarus
2019-02-04 10:09 ` Tudor.Ambarus
2019-02-04 14:00 ` Boris Brezillon [this message]
2019-02-04 14:00 ` Boris Brezillon
2019-02-04 14:00 ` Boris Brezillon
2019-02-04 14:00 ` Boris Brezillon
2019-02-04 10:09 ` [PATCH v4 02/13] spi: atmel-quadspi: order header files inclusion alphabetically Tudor.Ambarus
2019-02-04 10:09 ` Tudor.Ambarus
2019-02-04 10:09 ` Tudor.Ambarus
2019-02-04 10:09 ` Tudor.Ambarus
2019-02-04 10:09 ` [PATCH v4 03/13] spi: atmel-quadspi: drop wrappers for iomem accesses Tudor.Ambarus
2019-02-04 10:09 ` Tudor.Ambarus
2019-02-04 10:09 ` Tudor.Ambarus
2019-02-04 10:09 ` Tudor.Ambarus
2019-02-04 10:09 ` [PATCH v4 04/13] spi: atmel-quadspi: fix naming scheme Tudor.Ambarus
2019-02-04 10:09 ` Tudor.Ambarus
2019-02-04 10:09 ` Tudor.Ambarus
2019-02-04 10:09 ` Tudor.Ambarus
2019-02-04 10:09 ` [PATCH v4 05/13] spi: atmel-quadspi: remove unnecessary cast Tudor.Ambarus
2019-02-04 10:09 ` Tudor.Ambarus
2019-02-04 10:09 ` Tudor.Ambarus
2019-02-04 10:09 ` Tudor.Ambarus
2019-02-04 10:09 ` [PATCH v4 06/13] spi: atmel-quadspi: return appropriate error code Tudor.Ambarus
2019-02-04 10:09 ` Tudor.Ambarus
2019-02-04 10:09 ` Tudor.Ambarus
2019-02-04 10:09 ` Tudor.Ambarus
2019-02-04 10:09 ` [PATCH v4 07/13] spi: atmel-quadspi: switch to SPDX license identifiers Tudor.Ambarus
2019-02-04 10:09 ` Tudor.Ambarus
2019-02-04 10:09 ` Tudor.Ambarus
2019-02-04 10:09 ` Tudor.Ambarus
2019-02-04 10:09 ` [PATCH v4 08/13] spi: atmel-quadspi: rework transfer macros Tudor.Ambarus
2019-02-04 10:09 ` Tudor.Ambarus
2019-02-04 10:09 ` Tudor.Ambarus
2019-02-04 10:09 ` Tudor.Ambarus
2019-02-04 14:01 ` Boris Brezillon
2019-02-04 14:01 ` Boris Brezillon
2019-02-04 14:01 ` Boris Brezillon
2019-02-04 14:01 ` Boris Brezillon
2019-02-04 10:09 ` [PATCH v4 09/13] dt-bindings: spi: atmel-quadspi: update example to new clock binding Tudor.Ambarus
2019-02-04 10:09 ` Tudor.Ambarus
2019-02-04 10:09 ` Tudor.Ambarus
2019-02-04 10:09 ` Tudor.Ambarus
2019-02-04 10:10 ` [PATCH v4 10/13] dt-bindings: spi: atmel-quadspi: make "pclk" mandatory Tudor.Ambarus
2019-02-04 10:10 ` Tudor.Ambarus
2019-02-04 10:10 ` Tudor.Ambarus
2019-02-04 10:10 ` Tudor.Ambarus
2019-02-04 10:10 ` [PATCH v4 11/13] spi: atmel-quadspi: add support for named peripheral clock Tudor.Ambarus
2019-02-04 10:10 ` Tudor.Ambarus
2019-02-04 10:10 ` Tudor.Ambarus
2019-02-04 10:10 ` Tudor.Ambarus
2019-02-04 10:10 ` [PATCH v4 12/13] dt-bindings: spi: atmel-quadspi: QuadSPI driver for Microchip SAM9X60 Tudor.Ambarus
2019-02-04 10:10 ` Tudor.Ambarus
2019-02-04 10:10 ` Tudor.Ambarus
2019-02-04 10:10 ` Tudor.Ambarus
2019-02-04 10:10 ` [PATCH v4 13/13] spi: atmel-quadspi: add support for sam9x60 qspi controller Tudor.Ambarus
2019-02-04 10:10 ` Tudor.Ambarus
2019-02-04 10:10 ` Tudor.Ambarus
2019-02-04 10:10 ` Tudor.Ambarus
2019-02-04 14:16 ` Boris Brezillon
2019-02-04 14:16 ` Boris Brezillon
2019-02-04 14:16 ` Boris Brezillon
2019-02-04 14:16 ` Boris Brezillon
2019-02-04 14:16 ` Boris Brezillon
2019-02-04 14:28 ` Tudor.Ambarus
2019-02-04 14:28 ` Tudor.Ambarus
2019-02-04 14:28 ` Tudor.Ambarus
2019-02-04 14:28 ` Tudor.Ambarus
2019-02-04 14:37 ` Boris Brezillon
2019-02-04 14:37 ` Boris Brezillon
2019-02-04 14:37 ` Boris Brezillon
2019-02-04 14:37 ` Boris Brezillon
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