From: Yangtao Li <tiny.windzz@gmail.com>
To: maxime.ripard@bootlin.com, wens@csie.org, robh+dt@kernel.org
Cc: mark.rutland@arm.com, linux-arm-kernel@lists.infradead.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Yangtao Li <tiny.windzz@gmail.com>
Subject: [PATCH 4/4] arm64: dts: allwinner: h6: Add CPU Operating Performance Points table
Date: Thu, 14 Feb 2019 08:09:10 -0500 [thread overview]
Message-ID: <20190214130910.9201-5-tiny.windzz@gmail.com> (raw)
In-Reply-To: <20190214130910.9201-1-tiny.windzz@gmail.com>
Add an OPP (Operating Performance Points) table for the CPU cores to
enable DVFS (Dynamic Voltage & Frequency Scaling) on the H6. This
information comes from github.
Signed-off-by: Yangtao Li <tiny.windzz@gmail.com>
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 61 ++++++++++++++++++++
1 file changed, 61 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index 57a1390ecdc2..46a4a69eb38f 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -28,6 +28,8 @@
enable-method = "psci";
clocks = <&ccu CLK_CPUX>;
clock-latency-ns = <244144>; /* 8 32k periods */
+ operating-points-v2 = <&cpu_opp_table>;
+ #cooling-cells = <2>;
};
cpu1: cpu@1 {
@@ -37,6 +39,8 @@
enable-method = "psci";
clocks = <&ccu CLK_CPUX>;
clock-latency-ns = <244144>; /* 8 32k periods */
+ operating-points-v2 = <&cpu_opp_table>;
+ #cooling-cells = <2>;
};
cpu2: cpu@2 {
@@ -46,6 +50,8 @@
enable-method = "psci";
clocks = <&ccu CLK_CPUX>;
clock-latency-ns = <244144>; /* 8 32k periods */
+ operating-points-v2 = <&cpu_opp_table>;
+ #cooling-cells = <2>;
};
cpu3: cpu@3 {
@@ -55,6 +61,61 @@
enable-method = "psci";
clocks = <&ccu CLK_CPUX>;
clock-latency-ns = <244144>; /* 8 32k periods */
+ operating-points-v2 = <&cpu_opp_table>;
+ #cooling-cells = <2>;
+ };
+ };
+
+ cpu_opp_table: opp_table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp@480000000 {
+ opp-hz = /bits/ 64 <480000000>;
+ opp-microvolt = <800000 800000 880000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp@720000000 {
+ opp-hz = /bits/ 64 <720000000>;
+ opp-microvolt = <800000 800000 880000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp@816000000 {
+ opp-hz = /bits/ 64 <816000000>;
+ opp-microvolt = <800000 800000 880000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp@888000000 {
+ opp-hz = /bits/ 64 <888000000>;
+ opp-microvolt = <800000 800000 940000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp@1080000000 {
+ opp-hz = /bits/ 64 <1080000000>;
+ opp-microvolt = <840000 840000 1060000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp@1320000000 {
+ opp-hz = /bits/ 64 <1320000000>;
+ opp-microvolt = <900000 900000 1160000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp@1488000000 {
+ opp-hz = /bits/ 64 <1488000000>;
+ opp-microvolt = <960000 960000 1160000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp@1800000000 {
+ opp-hz = /bits/ 64 <1800000000>;
+ opp-microvolt = <1060000 1060000 1160000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
};
};
--
2.17.0
WARNING: multiple messages have this Message-ID (diff)
From: Yangtao Li <tiny.windzz@gmail.com>
To: maxime.ripard@bootlin.com, wens@csie.org, robh+dt@kernel.org
Cc: mark.rutland@arm.com, devicetree@vger.kernel.org,
Yangtao Li <tiny.windzz@gmail.com>,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH 4/4] arm64: dts: allwinner: h6: Add CPU Operating Performance Points table
Date: Thu, 14 Feb 2019 08:09:10 -0500 [thread overview]
Message-ID: <20190214130910.9201-5-tiny.windzz@gmail.com> (raw)
In-Reply-To: <20190214130910.9201-1-tiny.windzz@gmail.com>
Add an OPP (Operating Performance Points) table for the CPU cores to
enable DVFS (Dynamic Voltage & Frequency Scaling) on the H6. This
information comes from github.
Signed-off-by: Yangtao Li <tiny.windzz@gmail.com>
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 61 ++++++++++++++++++++
1 file changed, 61 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index 57a1390ecdc2..46a4a69eb38f 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -28,6 +28,8 @@
enable-method = "psci";
clocks = <&ccu CLK_CPUX>;
clock-latency-ns = <244144>; /* 8 32k periods */
+ operating-points-v2 = <&cpu_opp_table>;
+ #cooling-cells = <2>;
};
cpu1: cpu@1 {
@@ -37,6 +39,8 @@
enable-method = "psci";
clocks = <&ccu CLK_CPUX>;
clock-latency-ns = <244144>; /* 8 32k periods */
+ operating-points-v2 = <&cpu_opp_table>;
+ #cooling-cells = <2>;
};
cpu2: cpu@2 {
@@ -46,6 +50,8 @@
enable-method = "psci";
clocks = <&ccu CLK_CPUX>;
clock-latency-ns = <244144>; /* 8 32k periods */
+ operating-points-v2 = <&cpu_opp_table>;
+ #cooling-cells = <2>;
};
cpu3: cpu@3 {
@@ -55,6 +61,61 @@
enable-method = "psci";
clocks = <&ccu CLK_CPUX>;
clock-latency-ns = <244144>; /* 8 32k periods */
+ operating-points-v2 = <&cpu_opp_table>;
+ #cooling-cells = <2>;
+ };
+ };
+
+ cpu_opp_table: opp_table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp@480000000 {
+ opp-hz = /bits/ 64 <480000000>;
+ opp-microvolt = <800000 800000 880000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp@720000000 {
+ opp-hz = /bits/ 64 <720000000>;
+ opp-microvolt = <800000 800000 880000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp@816000000 {
+ opp-hz = /bits/ 64 <816000000>;
+ opp-microvolt = <800000 800000 880000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp@888000000 {
+ opp-hz = /bits/ 64 <888000000>;
+ opp-microvolt = <800000 800000 940000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp@1080000000 {
+ opp-hz = /bits/ 64 <1080000000>;
+ opp-microvolt = <840000 840000 1060000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp@1320000000 {
+ opp-hz = /bits/ 64 <1320000000>;
+ opp-microvolt = <900000 900000 1160000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp@1488000000 {
+ opp-hz = /bits/ 64 <1488000000>;
+ opp-microvolt = <960000 960000 1160000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp@1800000000 {
+ opp-hz = /bits/ 64 <1800000000>;
+ opp-microvolt = <1060000 1060000 1160000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
};
};
--
2.17.0
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next prev parent reply other threads:[~2019-02-14 13:09 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-02-14 13:09 [PATCH 0/4] arm64: dts: allwinner: h6: Enable CPU DVFS(cpufreq) Yangtao Li
2019-02-14 13:09 ` Yangtao Li
2019-02-14 13:09 ` Yangtao Li
2019-02-14 13:09 ` [PATCH 1/4] arm64: dts: allwinner: h6: orangepi: Add CPU supply regulator Yangtao Li
2019-02-14 13:09 ` Yangtao Li
2019-02-14 13:46 ` Maxime Ripard
2019-02-14 13:46 ` Maxime Ripard
2019-02-14 14:07 ` Frank Lee
2019-02-14 14:07 ` Frank Lee
2019-02-14 14:35 ` Maxime Ripard
2019-02-14 14:35 ` Maxime Ripard
2019-02-14 13:09 ` [PATCH 2/4] arm64: dts: allwinner: h6: pine: " Yangtao Li
2019-02-14 13:09 ` Yangtao Li
2019-02-14 13:09 ` [PATCH 3/4] arm64: dts: allwinner: h6: Add clock to CPU cores Yangtao Li
2019-02-14 13:09 ` Yangtao Li
2019-02-14 13:09 ` Yangtao Li [this message]
2019-02-14 13:09 ` [PATCH 4/4] arm64: dts: allwinner: h6: Add CPU Operating Performance Points table Yangtao Li
2019-02-14 14:38 ` Maxime Ripard
2019-02-14 14:38 ` Maxime Ripard
2019-02-14 14:38 ` Maxime Ripard
2019-02-14 14:52 ` Frank Lee
2019-02-14 14:52 ` Frank Lee
2019-02-14 16:56 ` Frank Lee
2019-02-14 16:56 ` Frank Lee
2019-02-15 13:56 ` Maxime Ripard
2019-02-15 13:56 ` Maxime Ripard
2019-02-15 14:09 ` Frank Lee
2019-02-15 14:09 ` Frank Lee
2019-02-18 9:33 ` Maxime Ripard
2019-02-18 9:33 ` Maxime Ripard
2019-02-15 13:53 ` Maxime Ripard
2019-02-15 13:53 ` Maxime Ripard
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