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From: Rodrigo Vivi <rodrigo.vivi@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Subject: [CI 3/6] drm/i915/ehl: Add dpll mgr
Date: Thu, 21 Mar 2019 17:03:47 -0700	[thread overview]
Message-ID: <20190322000350.1233-3-rodrigo.vivi@intel.com> (raw)
In-Reply-To: <20190322000350.1233-1-rodrigo.vivi@intel.com>

From: Lucas De Marchi <lucas.demarchi@intel.com>

Elkhart Lake has a different set of PLLs as compared to Ice Lake,
although programming them is very similar.

v2: Rebase on top of s/icl_pll_funcs/combo_pll_funcs

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_dpll_mgr.c | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index dfe6a7114d56..eeb659946203 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -3245,6 +3245,18 @@ static const struct intel_dpll_mgr icl_pll_mgr = {
 	.dump_hw_state = icl_dump_hw_state,
 };
 
+static const struct dpll_info ehl_plls[] = {
+	{ "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
+	{ "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
+	{ },
+};
+
+static const struct intel_dpll_mgr ehl_pll_mgr = {
+	.dpll_info = ehl_plls,
+	.get_dpll = icl_get_dpll,
+	.dump_hw_state = icl_dump_hw_state,
+};
+
 /**
  * intel_shared_dpll_init - Initialize shared DPLLs
  * @dev: drm device
@@ -3258,7 +3270,9 @@ void intel_shared_dpll_init(struct drm_device *dev)
 	const struct dpll_info *dpll_info;
 	int i;
 
-	if (INTEL_GEN(dev_priv) >= 11)
+	if (IS_ELKHARTLAKE(dev_priv))
+		dpll_mgr = &ehl_pll_mgr;
+	else if (INTEL_GEN(dev_priv) >= 11)
 		dpll_mgr = &icl_pll_mgr;
 	else if (IS_CANNONLAKE(dev_priv))
 		dpll_mgr = &cnl_pll_mgr;
-- 
2.20.1

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  parent reply	other threads:[~2019-03-22  0:03 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-03-22  0:03 [CI 1/6] drm/i915/ehl: Add EHL platform info and PCI IDs Rodrigo Vivi
2019-03-22  0:03 ` [CI 2/6] drm/i915/ehl: Add ElkhartLake platform Rodrigo Vivi
2019-03-22  0:03 ` Rodrigo Vivi [this message]
2019-03-22  0:03 ` [CI 4/6] drm/i915/ehl: EHL outputs are different from ICL Rodrigo Vivi
2019-03-22  9:28   ` Jani Nikula
2019-03-22  0:03 ` [CI 5/6] drm/i915/ehl: Set proper eu slice/subslice parameters for EHL Rodrigo Vivi
2019-03-22  0:03 ` [CI 6/6] drm/i915/ehl: Add Support for DMC on EHL Rodrigo Vivi
2019-03-22  0:08 ` [PATCH] drm/i915/ehl: Add EHL platform info and PCI IDs Rodrigo Vivi
2019-03-22  2:04 ` ✗ Fi.CI.BAT: failure for series starting with drm/i915/ehl: Add EHL platform info and PCI IDs (rev2) Patchwork
  -- strict thread matches above, loose matches on Subject: below --
2019-03-22 17:58 [CI 1/6] drm/i915/ehl: Add EHL platform info and PCI IDs Rodrigo Vivi
2019-03-22 17:58 ` [CI 3/6] drm/i915/ehl: Add dpll mgr Rodrigo Vivi
2019-03-15 17:57 [CI 1/6] drm/i915/ehl: Add EHL platform info and PCI IDs Rodrigo Vivi
2019-03-15 17:57 ` [CI 3/6] drm/i915/ehl: Add dpll mgr Rodrigo Vivi
2019-03-16  0:18   ` Lucas De Marchi

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