From: Vidya Sagar <vidyas@nvidia.com>
To: lorenzo.pieralisi@arm.com, bhelgaas@google.com,
robh+dt@kernel.org, mark.rutland@arm.com,
thierry.reding@gmail.com, jonathanh@nvidia.com, kishon@ti.com,
catalin.marinas@arm.com, will.deacon@arm.com,
jingoohan1@gmail.com, gustavo.pimentel@synopsys.com
Cc: digetx@gmail.com, mperttunen@nvidia.com,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, kthota@nvidia.com,
mmaddireddy@nvidia.com, vidyas@nvidia.com, sagar.tv@gmail.com
Subject: [PATCH V10 06/15] dt-bindings: PCI: designware: Add binding for CDM register check
Date: Wed, 12 Jun 2019 15:23:30 +0530 [thread overview]
Message-ID: <20190612095339.20118-7-vidyas@nvidia.com> (raw)
In-Reply-To: <20190612095339.20118-1-vidyas@nvidia.com>
Add support to enable CDM (Configuration Dependent Module) registers check
for any data corruption. CDM registers include standard PCIe configuration
space registers, Port Logic registers and iATU and DMA registers.
Refer Section S.4 of Synopsys DesignWare Cores PCI Express Controller Databook
Version 4.90a
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
Changes since [v9]:
* None
Changes since [v8]:
* None
Changes since [v7]:
* None
Changes since [v6]:
* Changed "enable-cdm-check" to "snps,enable-cdm-check"
Changes since [v5]:
* None
Changes since [v4]:
* None
Changes since [v3]:
* None
Changes since [v2]:
* Changed flag name from 'cdm-check' to 'enable-cdm-check'
* Added info about Port Logic and DMA registers being part of CDM
Changes since [v1]:
* This is a new patch in v2 series
Documentation/devicetree/bindings/pci/designware-pcie.txt | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt
index 5561a1c060d0..3fba04da6a59 100644
--- a/Documentation/devicetree/bindings/pci/designware-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt
@@ -34,6 +34,11 @@ Optional properties:
- clock-names: Must include the following entries:
- "pcie"
- "pcie_bus"
+- snps,enable-cdm-check: This is a boolean property and if present enables
+ automatic checking of CDM (Configuration Dependent Module) registers
+ for data corruption. CDM registers include standard PCIe configuration
+ space registers, Port Logic registers, DMA and iATU (internal Address
+ Translation Unit) registers.
RC mode:
- num-viewport: number of view ports configured in hardware. If a platform
does not specify it, the driver assumes 2.
--
2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Vidya Sagar <vidyas@nvidia.com>
To: <lorenzo.pieralisi@arm.com>, <bhelgaas@google.com>,
<robh+dt@kernel.org>, <mark.rutland@arm.com>,
<thierry.reding@gmail.com>, <jonathanh@nvidia.com>,
<kishon@ti.com>, <catalin.marinas@arm.com>, <will.deacon@arm.com>,
<jingoohan1@gmail.com>, <gustavo.pimentel@synopsys.com>
Cc: <digetx@gmail.com>, <mperttunen@nvidia.com>,
<linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>, <kthota@nvidia.com>,
<mmaddireddy@nvidia.com>, <vidyas@nvidia.com>,
<sagar.tv@gmail.com>
Subject: [PATCH V10 06/15] dt-bindings: PCI: designware: Add binding for CDM register check
Date: Wed, 12 Jun 2019 15:23:30 +0530 [thread overview]
Message-ID: <20190612095339.20118-7-vidyas@nvidia.com> (raw)
In-Reply-To: <20190612095339.20118-1-vidyas@nvidia.com>
Add support to enable CDM (Configuration Dependent Module) registers check
for any data corruption. CDM registers include standard PCIe configuration
space registers, Port Logic registers and iATU and DMA registers.
Refer Section S.4 of Synopsys DesignWare Cores PCI Express Controller Databook
Version 4.90a
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
Changes since [v9]:
* None
Changes since [v8]:
* None
Changes since [v7]:
* None
Changes since [v6]:
* Changed "enable-cdm-check" to "snps,enable-cdm-check"
Changes since [v5]:
* None
Changes since [v4]:
* None
Changes since [v3]:
* None
Changes since [v2]:
* Changed flag name from 'cdm-check' to 'enable-cdm-check'
* Added info about Port Logic and DMA registers being part of CDM
Changes since [v1]:
* This is a new patch in v2 series
Documentation/devicetree/bindings/pci/designware-pcie.txt | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt
index 5561a1c060d0..3fba04da6a59 100644
--- a/Documentation/devicetree/bindings/pci/designware-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt
@@ -34,6 +34,11 @@ Optional properties:
- clock-names: Must include the following entries:
- "pcie"
- "pcie_bus"
+- snps,enable-cdm-check: This is a boolean property and if present enables
+ automatic checking of CDM (Configuration Dependent Module) registers
+ for data corruption. CDM registers include standard PCIe configuration
+ space registers, Port Logic registers, DMA and iATU (internal Address
+ Translation Unit) registers.
RC mode:
- num-viewport: number of view ports configured in hardware. If a platform
does not specify it, the driver assumes 2.
--
2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Vidya Sagar <vidyas@nvidia.com>
To: <lorenzo.pieralisi@arm.com>, <bhelgaas@google.com>,
<robh+dt@kernel.org>, <mark.rutland@arm.com>,
<thierry.reding@gmail.com>, <jonathanh@nvidia.com>,
<kishon@ti.com>, <catalin.marinas@arm.com>, <will.deacon@arm.com>,
<jingoohan1@gmail.com>, <gustavo.pimentel@synopsys.com>
Cc: devicetree@vger.kernel.org, mmaddireddy@nvidia.com,
kthota@nvidia.com, linux-pci@vger.kernel.org,
linux-kernel@vger.kernel.org, mperttunen@nvidia.com,
linux-tegra@vger.kernel.org, digetx@gmail.com, vidyas@nvidia.com,
linux-arm-kernel@lists.infradead.org, sagar.tv@gmail.com
Subject: [PATCH V10 06/15] dt-bindings: PCI: designware: Add binding for CDM register check
Date: Wed, 12 Jun 2019 15:23:30 +0530 [thread overview]
Message-ID: <20190612095339.20118-7-vidyas@nvidia.com> (raw)
In-Reply-To: <20190612095339.20118-1-vidyas@nvidia.com>
Add support to enable CDM (Configuration Dependent Module) registers check
for any data corruption. CDM registers include standard PCIe configuration
space registers, Port Logic registers and iATU and DMA registers.
Refer Section S.4 of Synopsys DesignWare Cores PCI Express Controller Databook
Version 4.90a
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
Changes since [v9]:
* None
Changes since [v8]:
* None
Changes since [v7]:
* None
Changes since [v6]:
* Changed "enable-cdm-check" to "snps,enable-cdm-check"
Changes since [v5]:
* None
Changes since [v4]:
* None
Changes since [v3]:
* None
Changes since [v2]:
* Changed flag name from 'cdm-check' to 'enable-cdm-check'
* Added info about Port Logic and DMA registers being part of CDM
Changes since [v1]:
* This is a new patch in v2 series
Documentation/devicetree/bindings/pci/designware-pcie.txt | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt
index 5561a1c060d0..3fba04da6a59 100644
--- a/Documentation/devicetree/bindings/pci/designware-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt
@@ -34,6 +34,11 @@ Optional properties:
- clock-names: Must include the following entries:
- "pcie"
- "pcie_bus"
+- snps,enable-cdm-check: This is a boolean property and if present enables
+ automatic checking of CDM (Configuration Dependent Module) registers
+ for data corruption. CDM registers include standard PCIe configuration
+ space registers, Port Logic registers, DMA and iATU (internal Address
+ Translation Unit) registers.
RC mode:
- num-viewport: number of view ports configured in hardware. If a platform
does not specify it, the driver assumes 2.
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2019-06-12 9:53 UTC|newest]
Thread overview: 73+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-12 9:53 [PATCH V10 00/15] Add Tegra194 PCIe support Vidya Sagar
2019-06-12 9:53 ` Vidya Sagar
2019-06-12 9:53 ` Vidya Sagar
2019-06-12 9:53 ` [PATCH V10 01/15] PCI: Add #defines for some of PCIe spec r4.0 features Vidya Sagar
2019-06-12 9:53 ` Vidya Sagar
2019-06-12 9:53 ` Vidya Sagar
2019-06-12 9:53 ` [PATCH V10 02/15] PCI: Disable MSI for Tegra194 root port Vidya Sagar
2019-06-12 9:53 ` Vidya Sagar
2019-06-12 9:53 ` Vidya Sagar
2019-06-12 9:53 ` [PATCH V10 03/15] PCI: dwc: Perform dbi regs write lock towards the end Vidya Sagar
2019-06-12 9:53 ` Vidya Sagar
2019-06-12 9:53 ` Vidya Sagar
2019-06-18 6:34 ` Jingoo Han
2019-06-18 6:34 ` Jingoo Han
2019-06-18 6:34 ` Jingoo Han
2019-06-12 9:53 ` [PATCH V10 04/15] PCI: dwc: Move config space capability search API Vidya Sagar
2019-06-12 9:53 ` Vidya Sagar
2019-06-12 9:53 ` Vidya Sagar
2019-06-12 9:53 ` [PATCH V10 05/15] PCI: dwc: Add ext " Vidya Sagar
2019-06-12 9:53 ` Vidya Sagar
2019-06-12 9:53 ` Vidya Sagar
2019-06-12 9:53 ` Vidya Sagar [this message]
2019-06-12 9:53 ` [PATCH V10 06/15] dt-bindings: PCI: designware: Add binding for CDM register check Vidya Sagar
2019-06-12 9:53 ` Vidya Sagar
2019-06-12 9:53 ` [PATCH V10 07/15] PCI: dwc: Add support to enable " Vidya Sagar
2019-06-12 9:53 ` Vidya Sagar
2019-06-12 9:53 ` Vidya Sagar
2019-06-12 9:53 ` [PATCH V10 08/15] dt-bindings: Add PCIe supports-clkreq property Vidya Sagar
2019-06-12 9:53 ` Vidya Sagar
2019-06-12 9:53 ` Vidya Sagar
2019-06-12 9:53 ` [PATCH V10 09/15] dt-bindings: PCI: tegra: Add device tree support for Tegra194 Vidya Sagar
2019-06-12 9:53 ` Vidya Sagar
2019-06-12 9:53 ` Vidya Sagar
2019-06-12 9:53 ` [PATCH V10 10/15] dt-bindings: PHY: P2U: Add Tegra194 P2U block Vidya Sagar
2019-06-12 9:53 ` Vidya Sagar
2019-06-12 9:53 ` Vidya Sagar
2019-06-20 7:22 ` Kishon Vijay Abraham I
2019-06-20 7:22 ` Kishon Vijay Abraham I
2019-06-20 7:22 ` Kishon Vijay Abraham I
2019-06-12 9:53 ` [PATCH V10 11/15] arm64: tegra: Add P2U and PCIe controller nodes to Tegra194 DT Vidya Sagar
2019-06-12 9:53 ` Vidya Sagar
2019-06-12 9:53 ` Vidya Sagar
2019-06-20 10:55 ` Thierry Reding
2019-06-20 10:55 ` Thierry Reding
2019-06-24 7:32 ` Vidya Sagar
2019-06-24 7:32 ` Vidya Sagar
2019-06-24 7:32 ` Vidya Sagar
2019-06-25 7:33 ` Thierry Reding
2019-06-25 7:33 ` Thierry Reding
2019-06-12 9:53 ` [PATCH V10 12/15] arm64: tegra: Enable PCIe slots in P2972-0000 board Vidya Sagar
2019-06-12 9:53 ` Vidya Sagar
2019-06-12 9:53 ` Vidya Sagar
2019-06-20 11:01 ` Thierry Reding
2019-06-20 11:01 ` Thierry Reding
2019-06-12 9:53 ` [PATCH V10 13/15] phy: tegra: Add PCIe PIPE2UPHY support Vidya Sagar
2019-06-12 9:53 ` Vidya Sagar
2019-06-12 9:53 ` Vidya Sagar
2019-06-20 7:24 ` Kishon Vijay Abraham I
2019-06-20 7:24 ` Kishon Vijay Abraham I
2019-06-20 7:24 ` Kishon Vijay Abraham I
2019-06-20 23:23 ` Dmitry Osipenko
2019-06-20 23:23 ` Dmitry Osipenko
2019-06-22 17:56 ` Vidya Sagar
2019-06-22 17:56 ` Vidya Sagar
2019-06-22 17:56 ` Vidya Sagar
2019-06-12 9:53 ` [PATCH V10 14/15] PCI: tegra: Add Tegra194 PCIe support Vidya Sagar
2019-06-12 9:53 ` Vidya Sagar
2019-06-12 9:53 ` Vidya Sagar
2019-06-12 9:53 ` [PATCH V10 15/15] arm64: Add Tegra194 PCIe driver to defconfig Vidya Sagar
2019-06-12 9:53 ` Vidya Sagar
2019-06-12 9:53 ` Vidya Sagar
2019-06-20 11:03 ` Thierry Reding
2019-06-20 11:03 ` Thierry Reding
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