Re: [PATCH V6 20/27] PCI: tegra: Disable MSI for Tegra PCIe root port

From: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
To: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Cc: Bjorn Helgaas <helgaas@kernel.org>,
	thierry.reding@gmail.com, robh+dt@kernel.org,
	mark.rutland@arm.com, jonathanh@nvidia.com, vidyas@nvidia.com,
	linux-tegra@vger.kernel.org, linux-pci@vger.kernel.org,
	devicetree@vger.kernel.org
Subject: Re: [PATCH V6 20/27] PCI: tegra: Disable MSI for Tegra PCIe root port
Date: Wed, 19 Jun 2019 10:50:52 +0100	[thread overview]
Message-ID: <20190619095052.GB10372@e121166-lin.cambridge.arm.com> (raw)
In-Reply-To: <e06f85eb-be0c-c2a5-84a9-51aa9b8372c3@nvidia.com>

On Wed, Jun 19, 2019 at 09:25:54AM +0530, Manikanta Maddireddy wrote:

[...]

> > s/msi/MSI/
> >
> > What's going on here?  Vidya posted a very similar patch [1] (although
> 
> This series is focused on Tegra20, Tegra30, Tegra124, Tegra210 and Tegra186,
> whereas Vidya's series is focused only on Tegra194. So I didn't include
> Tegra194 device IDs.
> 
> > his included nice spec citations, which you omitted), but his added
> > quirks for 0x1ad0, 0x1ad1, and 0x1ad2.  You didn't include any of
> > those here.
> >
> > Maybe Lorenzo will sort this all out, but it would make things easier
> > if you and Vidya got together and integrated your patches yourselves
> > so Lorenzo didn't have to worry about it.
> >
> > [1] https://lore.kernel.org/lkml/20190612095339.20118-3-vidyas@nvidia.com
> 
> I talked with Vidya, he will take this changes in his series if he needs
> to publish another version, or else he will publish a new patch to add
> quirk for legacy Tegra SOCs.
> 
> Lorenzo,
> If this series is ready for integration, please drop this patch.

OK, will do.

Thanks,
Lorenzo

> Manikanta
> 
> >
> >> + */
> >> +static void pci_quirk_nvidia_tegra_disable_rp_msi(struct pci_dev *dev)
> >> +{
> >> +	dev->no_msi = 1;
> >> +}
> >> +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0,
> >> +			      PCI_CLASS_BRIDGE_PCI, 8,
> >> +			      pci_quirk_nvidia_tegra_disable_rp_msi);
> >> +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1,
> >> +			      PCI_CLASS_BRIDGE_PCI, 8,
> >> +			      pci_quirk_nvidia_tegra_disable_rp_msi);
> >> +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1c,
> >> +			      PCI_CLASS_BRIDGE_PCI, 8,
> >> +			      pci_quirk_nvidia_tegra_disable_rp_msi);
> >> +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1d,
> >> +			      PCI_CLASS_BRIDGE_PCI, 8,
> >> +			      pci_quirk_nvidia_tegra_disable_rp_msi);
> >> +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e12,
> >> +			      PCI_CLASS_BRIDGE_PCI, 8,
> >> +			      pci_quirk_nvidia_tegra_disable_rp_msi);
> >> +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e13,
> >> +			      PCI_CLASS_BRIDGE_PCI, 8,
> >> +			      pci_quirk_nvidia_tegra_disable_rp_msi);
> >> +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0fae,
> >> +			      PCI_CLASS_BRIDGE_PCI, 8,
> >> +			      pci_quirk_nvidia_tegra_disable_rp_msi);
> >> +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0faf,
> >> +			      PCI_CLASS_BRIDGE_PCI, 8,
> >> +			      pci_quirk_nvidia_tegra_disable_rp_msi);
> >> +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e5,
> >> +			      PCI_CLASS_BRIDGE_PCI, 8,
> >> +			      pci_quirk_nvidia_tegra_disable_rp_msi);
> >> +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e6,
> >> +			      PCI_CLASS_BRIDGE_PCI, 8,
> >> +			      pci_quirk_nvidia_tegra_disable_rp_msi);
> >> +
> >>  /*
> >>   * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing
> >>   * config register.  This register controls the routing of legacy
> >> -- 
> >> 2.17.1
> >>
> 