From: Rodrigo Vivi <rodrigo.vivi@intel.com> To: "Souza, Jose" <jose.souza@intel.com> Cc: "gregkh@linuxfoundation.org" <gregkh@linuxfoundation.org>, "Pandiyan, Dhinakaran" <dhinakaran.pandiyan@intel.com>, "sashal@kernel.org" <sashal@kernel.org>, "intel-gfx@lists.freedesktop.org" <intel-gfx@lists.freedesktop.org>, "stable@vger.kernel.org" <stable@vger.kernel.org>, Jani Nikula <jani.nikula@intel.com>, Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Subject: Re: [Intel-gfx] [PATCH stable v5.2] drm/i915/vbt: Fix VBT parsing for the PSR section Date: Wed, 24 Jul 2019 10:40:29 -0700 [thread overview] Message-ID: <20190724174029.GC30776@intel.com> (raw) In-Reply-To: <05339e812e35a4cf1811f26a06bd5a4d1d652407.camel@intel.com> On Wed, Jul 24, 2019 at 05:27:42PM +0000, Souza, Jose wrote: > On Wed, 2019-07-24 at 14:06 +0200, Greg KH wrote: > > On Mon, Jul 22, 2019 at 04:13:25PM -0700, Dhinakaran Pandiyan wrote: > > > A single 32-bit PSR2 training pattern field follows the sixteen > > > element > > > array of PSR table entries in the VBT spec. But, we incorrectly > > > define > > > this PSR2 field for each of the PSR table entries. As a result, the > > > PSR1 > > > training pattern duration for any panel_type != 0 will be parsed > > > incorrectly. Secondly, PSR2 training pattern durations for VBTs > > > with bdb > > > version >= 226 will also be wrong. > > > > > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> > > > Cc: José Roberto de Souza <jose.souza@intel.com> > > > Cc: stable@vger.kernel.org > > > Cc: stable@vger.kernel.org #v5.2 > > > Fixes: 88a0d9606aff ("drm/i915/vbt: Parse and use the new field > > > with PSR2 TP2/3 wakeup time") > > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111088 > > > Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=204183 > > > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> > > > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > Reviewed-by: José Roberto de Souza <jose.souza@intel.com> > > > Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > > > Tested-by: François Guerraz <kubrick@fgv6.net> > > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > > > Link: > > > https://patchwork.freedesktop.org/patch/msgid/20190717223451.2595-1-dhinakaran.pandiyan@intel.com > > > (cherry picked from commit > > > b5ea9c9337007d6e700280c8a60b4e10d070fb53) > > > > There is no such commit in Linus's kernel tree :( not yet... It is queued for 5.3 on drm-intel-next-queued. This line is automatically added by "dim" tool when cherry-picking queued stuff for our drm-intel fixes branches. > > > > It is still on drm-intel/drm-intel-next-queued - > ssh://git.freedesktop.org/git/drm-intel > > Rodrigo do you know when is the next pull-request to Linus? I will start doing the pull requests to Dave and Daniel soon, but this doesn't reach Linus tree before next merge window. Eventually it will be there. If this is a blocker fell free to remove the line and merge the patch please, because this fix very critical issue that impact users. So we can continue the discussion in parallel on how to handle commit links like this in a better way. Thanks, Rodrigo. > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
WARNING: multiple messages have this Message-ID (diff)
From: Rodrigo Vivi <rodrigo.vivi@intel.com> To: "Souza, Jose" <jose.souza@intel.com> Cc: "sashal@kernel.org" <sashal@kernel.org>, Jani Nikula <jani.nikula@intel.com>, "gregkh@linuxfoundation.org" <gregkh@linuxfoundation.org>, "intel-gfx@lists.freedesktop.org" <intel-gfx@lists.freedesktop.org>, "stable@vger.kernel.org" <stable@vger.kernel.org>, "Pandiyan, Dhinakaran" <dhinakaran.pandiyan@intel.com> Subject: Re: [PATCH stable v5.2] drm/i915/vbt: Fix VBT parsing for the PSR section Date: Wed, 24 Jul 2019 10:40:29 -0700 [thread overview] Message-ID: <20190724174029.GC30776@intel.com> (raw) In-Reply-To: <05339e812e35a4cf1811f26a06bd5a4d1d652407.camel@intel.com> On Wed, Jul 24, 2019 at 05:27:42PM +0000, Souza, Jose wrote: > On Wed, 2019-07-24 at 14:06 +0200, Greg KH wrote: > > On Mon, Jul 22, 2019 at 04:13:25PM -0700, Dhinakaran Pandiyan wrote: > > > A single 32-bit PSR2 training pattern field follows the sixteen > > > element > > > array of PSR table entries in the VBT spec. But, we incorrectly > > > define > > > this PSR2 field for each of the PSR table entries. As a result, the > > > PSR1 > > > training pattern duration for any panel_type != 0 will be parsed > > > incorrectly. Secondly, PSR2 training pattern durations for VBTs > > > with bdb > > > version >= 226 will also be wrong. > > > > > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> > > > Cc: José Roberto de Souza <jose.souza@intel.com> > > > Cc: stable@vger.kernel.org > > > Cc: stable@vger.kernel.org #v5.2 > > > Fixes: 88a0d9606aff ("drm/i915/vbt: Parse and use the new field > > > with PSR2 TP2/3 wakeup time") > > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111088 > > > Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=204183 > > > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> > > > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > Reviewed-by: José Roberto de Souza <jose.souza@intel.com> > > > Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > > > Tested-by: François Guerraz <kubrick@fgv6.net> > > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > > > Link: > > > https://patchwork.freedesktop.org/patch/msgid/20190717223451.2595-1-dhinakaran.pandiyan@intel.com > > > (cherry picked from commit > > > b5ea9c9337007d6e700280c8a60b4e10d070fb53) > > > > There is no such commit in Linus's kernel tree :( not yet... It is queued for 5.3 on drm-intel-next-queued. This line is automatically added by "dim" tool when cherry-picking queued stuff for our drm-intel fixes branches. > > > > It is still on drm-intel/drm-intel-next-queued - > ssh://git.freedesktop.org/git/drm-intel > > Rodrigo do you know when is the next pull-request to Linus? I will start doing the pull requests to Dave and Daniel soon, but this doesn't reach Linus tree before next merge window. Eventually it will be there. If this is a blocker fell free to remove the line and merge the patch please, because this fix very critical issue that impact users. So we can continue the discussion in parallel on how to handle commit links like this in a better way. Thanks, Rodrigo. > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2019-07-24 17:39 UTC|newest] Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-07-17 22:34 [PATCH] drm/i915/vbt: Fix VBT parsing for the PSR section Dhinakaran Pandiyan 2019-07-17 22:34 ` Dhinakaran Pandiyan 2019-07-17 23:19 ` ✓ Fi.CI.BAT: success for drm/i915/vbt: Fix VBT parsing for the PSR section (rev3) Patchwork 2019-07-18 19:14 ` [Intel-gfx] [PATCH] drm/i915/vbt: Fix VBT parsing for the PSR section Rodrigo Vivi 2019-07-19 0:45 ` Sasha Levin 2019-07-22 23:13 ` [PATCH stable v5.2] " Dhinakaran Pandiyan 2019-07-24 12:06 ` Greg KH 2019-07-24 17:27 ` Souza, Jose 2019-07-24 17:27 ` Souza, Jose 2019-07-24 17:40 ` Rodrigo Vivi [this message] 2019-07-24 17:40 ` Rodrigo Vivi 2019-07-30 15:19 ` [Intel-gfx] " Rodrigo Vivi 2019-07-30 15:19 ` Rodrigo Vivi 2019-07-30 15:27 ` [Intel-gfx] " Greg KH 2019-07-30 16:22 ` Rodrigo Vivi 2019-07-30 16:27 ` Greg KH 2019-07-30 16:56 ` Rodrigo Vivi 2019-07-30 16:56 ` Rodrigo Vivi 2019-07-30 17:08 ` Greg KH 2019-07-30 18:24 ` Pandiyan, Dhinakaran 2019-07-30 20:42 ` [Intel-gfx] [PATCH] " Rodrigo Vivi 2019-07-30 21:48 ` Sasha Levin 2019-07-30 21:48 ` Sasha Levin 2019-07-31 17:14 ` [Intel-gfx] " Vivi, Rodrigo 2019-07-31 17:14 ` Vivi, Rodrigo 2019-07-31 19:23 ` [Intel-gfx] " Sasha Levin 2019-07-31 19:23 ` Sasha Levin
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