From: Icenowy Zheng <icenowy@aosc.io> To: Rob Herring <robh+dt@kernel.org>, Maxime Ripard <mripard@kernel.org>, Chen-Yu Tsai <wens@csie.org>, Linus Walleij <linus.walleij@linaro.org> Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com, Icenowy Zheng <icenowy@aosc.io> Subject: [PATCH v5 2/6] clk: sunxi-ng: v3s: add missing clock slices for MMC2 module clocks Date: Sun, 28 Jul 2019 11:12:23 +0800 [thread overview] Message-ID: <20190728031227.49140-3-icenowy@aosc.io> (raw) In-Reply-To: <20190728031227.49140-1-icenowy@aosc.io> The MMC2 clock slices are currently not defined in V3s CCU driver, which makes MMC2 not working. Fix this issue. Fixes: d0f11d14b0bc ("clk: sunxi-ng: add support for V3s CCU") Signed-off-by: Icenowy Zheng <icenowy@aosc.io> --- Changes in v5: - Fix typo on hw_clk reference. Patch introduced in v4. drivers/clk/sunxi-ng/ccu-sun8i-v3s.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c index 4eb68243e310..f79170e145df 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c @@ -513,6 +513,9 @@ static struct clk_hw_onecell_data sun8i_v3s_hw_clks = { [CLK_MMC1] = &mmc1_clk.common.hw, [CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw, [CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw, + [CLK_MMC2] = &mmc2_clk.common.hw, + [CLK_MMC2_SAMPLE] = &mmc2_sample_clk.common.hw, + [CLK_MMC2_OUTPUT] = &mmc2_output_clk.common.hw, [CLK_CE] = &ce_clk.common.hw, [CLK_SPI0] = &spi0_clk.common.hw, [CLK_USB_PHY0] = &usb_phy0_clk.common.hw, -- 2.21.0
WARNING: multiple messages have this Message-ID (diff)
From: Icenowy Zheng <icenowy@aosc.io> To: Rob Herring <robh+dt@kernel.org>, Maxime Ripard <mripard@kernel.org>, Chen-Yu Tsai <wens@csie.org>, Linus Walleij <linus.walleij@linaro.org> Cc: linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Icenowy Zheng <icenowy@aosc.io> Subject: [PATCH v5 2/6] clk: sunxi-ng: v3s: add missing clock slices for MMC2 module clocks Date: Sun, 28 Jul 2019 11:12:23 +0800 [thread overview] Message-ID: <20190728031227.49140-3-icenowy@aosc.io> (raw) In-Reply-To: <20190728031227.49140-1-icenowy@aosc.io> The MMC2 clock slices are currently not defined in V3s CCU driver, which makes MMC2 not working. Fix this issue. Fixes: d0f11d14b0bc ("clk: sunxi-ng: add support for V3s CCU") Signed-off-by: Icenowy Zheng <icenowy@aosc.io> --- Changes in v5: - Fix typo on hw_clk reference. Patch introduced in v4. drivers/clk/sunxi-ng/ccu-sun8i-v3s.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c index 4eb68243e310..f79170e145df 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c @@ -513,6 +513,9 @@ static struct clk_hw_onecell_data sun8i_v3s_hw_clks = { [CLK_MMC1] = &mmc1_clk.common.hw, [CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw, [CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw, + [CLK_MMC2] = &mmc2_clk.common.hw, + [CLK_MMC2_SAMPLE] = &mmc2_sample_clk.common.hw, + [CLK_MMC2_OUTPUT] = &mmc2_output_clk.common.hw, [CLK_CE] = &ce_clk.common.hw, [CLK_SPI0] = &spi0_clk.common.hw, [CLK_USB_PHY0] = &usb_phy0_clk.common.hw, -- 2.21.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2019-07-28 3:13 UTC|newest] Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-07-28 3:12 [PATCH v5 0/6] Support for Allwinner V3/S3L and Sochip S3 Icenowy Zheng 2019-07-28 3:12 ` Icenowy Zheng 2019-07-28 3:12 ` [PATCH v5 1/6] pinctrl: sunxi: v3s: introduce support for V3 Icenowy Zheng 2019-07-28 3:12 ` Icenowy Zheng 2019-08-05 10:36 ` Linus Walleij 2019-08-05 10:36 ` Linus Walleij 2019-07-28 3:12 ` Icenowy Zheng [this message] 2019-07-28 3:12 ` [PATCH v5 2/6] clk: sunxi-ng: v3s: add missing clock slices for MMC2 module clocks Icenowy Zheng 2019-07-28 3:12 ` [PATCH v5 3/6] clk: sunxi-ng: v3s: add Allwinner V3 support Icenowy Zheng 2019-07-28 3:12 ` Icenowy Zheng 2019-07-28 3:12 ` [PATCH v5 4/6] ARM: sunxi: dts: s3/s3l/v3: add DTSI files for S3/S3L/V3 SoCs Icenowy Zheng 2019-07-28 3:12 ` Icenowy Zheng 2019-07-28 3:12 ` [PATCH v5 5/6] dt-bindings: arm: sunxi: add binding for Lichee Zero Plus core board Icenowy Zheng 2019-07-28 3:12 ` Icenowy Zheng 2019-07-28 3:12 ` [PATCH v5 6/6] ARM: dts: sun8i: s3: add devicetree for Lichee zero plus w/ S3 Icenowy Zheng 2019-07-28 3:12 ` Icenowy Zheng 2019-08-12 8:07 ` [PATCH v5 0/6] Support for Allwinner V3/S3L and Sochip S3 Maxime Ripard 2019-08-12 8:07 ` Maxime Ripard
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