From: Brian Masney <masneyb@onstation.org> To: agross@kernel.org, robdclark@gmail.com, sean@poorly.run, robh+dt@kernel.org, bjorn.andersson@linaro.org Cc: airlied@linux.ie, daniel@ffwll.ch, mark.rutland@arm.com, jonathan@marek.ca, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, jcrouse@codeaurora.org Subject: [PATCH v5 1/7] dt-bindings: soc: qcom: add On Chip MEMory (OCMEM) bindings Date: Mon, 5 Aug 2019 20:22:23 -0400 [thread overview] Message-ID: <20190806002229.8304-2-masneyb@onstation.org> (raw) In-Reply-To: <20190806002229.8304-1-masneyb@onstation.org> Add device tree bindings for the On Chip Memory (OCMEM) that is present on some Qualcomm Snapdragon SoCs. Signed-off-by: Brian Masney <masneyb@onstation.org> Reviewed-by: Rob Herring <robh@kernel.org> --- Changes since v4: - remove qcom from path in $id Changes since v3: - add ranges property - remove unnecessary literal block | - add #address-cells and #size-cells to binding - rename path devicetree/bindings/sram/qcom/ to devicetree/bindings/sram/ since this is the only qcom binding in the sram namespace. That was a holdover from when I originally put this in the soc namespace. Changes since v2: - Add *-sram node and gmu-sram to example. Changes since v1: - Rename qcom,ocmem-msm8974 to qcom,msm8974-ocmem - Renamed reg-names to ctrl and mem - update hardware description - moved from soc to sram namespace in the device tree bindings .../devicetree/bindings/sram/qcom,ocmem.yaml | 96 +++++++++++++++++++ 1 file changed, 96 insertions(+) create mode 100644 Documentation/devicetree/bindings/sram/qcom,ocmem.yaml diff --git a/Documentation/devicetree/bindings/sram/qcom,ocmem.yaml b/Documentation/devicetree/bindings/sram/qcom,ocmem.yaml new file mode 100644 index 000000000000..222990f9923c --- /dev/null +++ b/Documentation/devicetree/bindings/sram/qcom,ocmem.yaml @@ -0,0 +1,96 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sram/qcom,ocmem.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: On Chip Memory (OCMEM) that is present on some Qualcomm Snapdragon SoCs. + +maintainers: + - Brian Masney <masneyb@onstation.org> + +description: | + The On Chip Memory (OCMEM) is typically used by the GPU, camera/video, and + audio components on some Snapdragon SoCs. + +properties: + compatible: + const: qcom,msm8974-ocmem + + reg: + items: + - description: Control registers + - description: OCMEM address range + + reg-names: + items: + - const: ctrl + - const: mem + + clocks: + items: + - description: Core clock + - description: Interface clock + + clock-names: + items: + - const: core + - const: iface + + '#address-cells': + const: 1 + + '#size-cells': + const: 1 + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - '#address-cells' + - '#size-cells' + +patternProperties: + "^.+-sram$": + type: object + description: A region of reserved memory. + + properties: + reg: + maxItems: 1 + + ranges: + maxItems: 1 + + required: + - reg + - ranges + +examples: + - | + #include <dt-bindings/clock/qcom,rpmcc.h> + #include <dt-bindings/clock/qcom,mmcc-msm8974.h> + + ocmem: ocmem@fdd00000 { + compatible = "qcom,msm8974-ocmem"; + + reg = <0xfdd00000 0x2000>, + <0xfec00000 0x180000>; + reg-names = "ctrl", + "mem"; + + clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>, + <&mmcc OCMEMCX_OCMEMNOC_CLK>; + clock-names = "core", + "iface"; + + #address-cells = <1>; + #size-cells = <1>; + + gmu-sram@0 { + reg = <0x0 0x100000>; + ranges = <0 0 0xfec00000 0x100000>; + }; + }; -- 2.21.0
WARNING: multiple messages have this Message-ID (diff)
From: Brian Masney <masneyb-1iNe0GrtECGEi8DpZVb4nw@public.gmane.org> To: agross-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, robdclark-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org, sean-p7yTbzM4H96eqtR555YLDQ@public.gmane.org, robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, bjorn.andersson-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org Cc: mark.rutland-5wv7dgnIgG8@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, jonathan-eSc4qw6YbEQ@public.gmane.org, airlied-cv59FeDIM0c@public.gmane.org, linux-arm-msm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org, jcrouse-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, daniel-/w4YWyX8dFk@public.gmane.org, freedreno-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Subject: [PATCH v5 1/7] dt-bindings: soc: qcom: add On Chip MEMory (OCMEM) bindings Date: Mon, 5 Aug 2019 20:22:23 -0400 [thread overview] Message-ID: <20190806002229.8304-2-masneyb@onstation.org> (raw) In-Reply-To: <20190806002229.8304-1-masneyb-1iNe0GrtECGEi8DpZVb4nw@public.gmane.org> Add device tree bindings for the On Chip Memory (OCMEM) that is present on some Qualcomm Snapdragon SoCs. Signed-off-by: Brian Masney <masneyb@onstation.org> Reviewed-by: Rob Herring <robh@kernel.org> --- Changes since v4: - remove qcom from path in $id Changes since v3: - add ranges property - remove unnecessary literal block | - add #address-cells and #size-cells to binding - rename path devicetree/bindings/sram/qcom/ to devicetree/bindings/sram/ since this is the only qcom binding in the sram namespace. That was a holdover from when I originally put this in the soc namespace. Changes since v2: - Add *-sram node and gmu-sram to example. Changes since v1: - Rename qcom,ocmem-msm8974 to qcom,msm8974-ocmem - Renamed reg-names to ctrl and mem - update hardware description - moved from soc to sram namespace in the device tree bindings .../devicetree/bindings/sram/qcom,ocmem.yaml | 96 +++++++++++++++++++ 1 file changed, 96 insertions(+) create mode 100644 Documentation/devicetree/bindings/sram/qcom,ocmem.yaml diff --git a/Documentation/devicetree/bindings/sram/qcom,ocmem.yaml b/Documentation/devicetree/bindings/sram/qcom,ocmem.yaml new file mode 100644 index 000000000000..222990f9923c --- /dev/null +++ b/Documentation/devicetree/bindings/sram/qcom,ocmem.yaml @@ -0,0 +1,96 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sram/qcom,ocmem.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: On Chip Memory (OCMEM) that is present on some Qualcomm Snapdragon SoCs. + +maintainers: + - Brian Masney <masneyb@onstation.org> + +description: | + The On Chip Memory (OCMEM) is typically used by the GPU, camera/video, and + audio components on some Snapdragon SoCs. + +properties: + compatible: + const: qcom,msm8974-ocmem + + reg: + items: + - description: Control registers + - description: OCMEM address range + + reg-names: + items: + - const: ctrl + - const: mem + + clocks: + items: + - description: Core clock + - description: Interface clock + + clock-names: + items: + - const: core + - const: iface + + '#address-cells': + const: 1 + + '#size-cells': + const: 1 + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - '#address-cells' + - '#size-cells' + +patternProperties: + "^.+-sram$": + type: object + description: A region of reserved memory. + + properties: + reg: + maxItems: 1 + + ranges: + maxItems: 1 + + required: + - reg + - ranges + +examples: + - | + #include <dt-bindings/clock/qcom,rpmcc.h> + #include <dt-bindings/clock/qcom,mmcc-msm8974.h> + + ocmem: ocmem@fdd00000 { + compatible = "qcom,msm8974-ocmem"; + + reg = <0xfdd00000 0x2000>, + <0xfec00000 0x180000>; + reg-names = "ctrl", + "mem"; + + clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>, + <&mmcc OCMEMCX_OCMEMNOC_CLK>; + clock-names = "core", + "iface"; + + #address-cells = <1>; + #size-cells = <1>; + + gmu-sram@0 { + reg = <0x0 0x100000>; + ranges = <0 0 0xfec00000 0x100000>; + }; + }; -- 2.21.0 _______________________________________________ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
next prev parent reply other threads:[~2019-08-06 0:23 UTC|newest] Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-08-06 0:22 [PATCH v5 0/7] qcom: add OCMEM support Brian Masney 2019-08-06 0:22 ` Brian Masney [this message] 2019-08-06 0:22 ` [PATCH v5 1/7] dt-bindings: soc: qcom: add On Chip MEMory (OCMEM) bindings Brian Masney 2019-08-06 0:22 ` [PATCH v5 2/7] dt-bindings: display: msm: gmu: add optional ocmem property Brian Masney 2019-08-06 0:22 ` Brian Masney 2019-08-21 19:26 ` Rob Herring 2019-08-21 19:26 ` Rob Herring 2019-08-21 19:38 ` Brian Masney 2019-08-06 0:22 ` [PATCH v5 3/7] firmware: qcom: scm: add OCMEM lock/unlock interface Brian Masney 2019-08-06 0:22 ` Brian Masney 2019-08-06 0:22 ` [PATCH v5 4/7] firmware: qcom: scm: add support to restore secure config to qcm_scm-32 Brian Masney 2019-08-06 0:22 ` Brian Masney 2019-08-06 0:22 ` [PATCH v5 5/7] soc: qcom: add OCMEM driver Brian Masney 2019-08-06 0:22 ` Brian Masney 2019-08-06 0:22 ` [PATCH v5 6/7] drm/msm/gpu: add ocmem init/cleanup functions Brian Masney 2019-08-06 0:22 ` Brian Masney 2019-08-06 0:22 ` [PATCH v5 7/7] ARM: qcom_defconfig: add ocmem support Brian Masney 2019-08-06 0:22 ` Brian Masney
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