From: Thierry Reding <thierry.reding@gmail.com>
To: Vidya Sagar <vidyas@nvidia.com>
Cc: mark.rutland@arm.com, devicetree@vger.kernel.org,
lorenzo.pieralisi@arm.com, mperttunen@nvidia.com,
mmaddireddy@nvidia.com, linux-pci@vger.kernel.org,
catalin.marinas@arm.com, will.deacon@arm.com,
linux-kernel@vger.kernel.org, kthota@nvidia.com, kishon@ti.com,
linux-tegra@vger.kernel.org, robh+dt@kernel.org,
gustavo.pimentel@synopsys.com, jingoohan1@gmail.com,
bhelgaas@google.com, digetx@gmail.com, jonathanh@nvidia.com,
linux-arm-kernel@lists.infradead.org, sagar.tv@gmail.com
Subject: Re: [PATCH V15 00/13] PCI: tegra: Add Tegra194 PCIe support
Date: Mon, 12 Aug 2019 12:25:19 +0200 [thread overview]
Message-ID: <20190812102519.GN8903@ulmo> (raw)
In-Reply-To: <20190809044609.20401-1-vidyas@nvidia.com>
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On Fri, Aug 09, 2019 at 10:15:56AM +0530, Vidya Sagar wrote:
> Tegra194 has six PCIe controllers based on Synopsys DesignWare core.
> There are two Universal PHY (UPHY) blocks with each supporting 12(HSIO:
> Hisg Speed IO) and 8(NVHS: NVIDIA High Speed) lanes respectively.
> Controllers:0~4 use UPHY lanes from HSIO brick whereas Controller:5 uses
> UPHY lanes from NVHS brick. Lane mapping in HSIO UPHY brick to each PCIe
> controller (0~4) is controlled in XBAR module by BPMP-FW. Since PCIe
> core has PIPE interface, a glue module called PIPE-to-UPHY (P2U) is used
> to connect each UPHY lane (applicable to both HSIO and NVHS UPHY bricks)
> to PCIe controller
> This patch series
> - Adds support for P2U PHY driver
> - Adds support for PCIe host controller
> - Adds device tree nodes each PCIe controllers
> - Enables nodes applicable to p2972-0000 platform
> - Adds helper APIs in Designware core driver to get capability regs offset
> - Adds defines for new feature registers of PCIe spec revision 4
> - Makes changes in DesignWare core driver to get Tegra194 PCIe working
>
> Testing done on P2972-0000 platform
> - Able to get PCIe link up with on-board Marvel eSATA controller
> - Able to get PCIe link up with NVMe cards connected to M.2 Key-M slot
> - Able to do data transfers with both SATA drives and NVMe cards
> - Able to perform suspend-resume sequence
Do you happen to have a patch for P2972-0000 PCI support? I don't see it
in this series.
Thierry
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WARNING: multiple messages have this Message-ID (diff)
From: Thierry Reding <thierry.reding@gmail.com>
To: Vidya Sagar <vidyas@nvidia.com>
Cc: lorenzo.pieralisi@arm.com, bhelgaas@google.com,
robh+dt@kernel.org, mark.rutland@arm.com, jonathanh@nvidia.com,
kishon@ti.com, catalin.marinas@arm.com, will.deacon@arm.com,
jingoohan1@gmail.com, gustavo.pimentel@synopsys.com,
digetx@gmail.com, mperttunen@nvidia.com,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, kthota@nvidia.com,
mmaddireddy@nvidia.com, sagar.tv@gmail.com
Subject: Re: [PATCH V15 00/13] PCI: tegra: Add Tegra194 PCIe support
Date: Mon, 12 Aug 2019 12:25:19 +0200 [thread overview]
Message-ID: <20190812102519.GN8903@ulmo> (raw)
In-Reply-To: <20190809044609.20401-1-vidyas@nvidia.com>
[-- Attachment #1: Type: text/plain, Size: 1502 bytes --]
On Fri, Aug 09, 2019 at 10:15:56AM +0530, Vidya Sagar wrote:
> Tegra194 has six PCIe controllers based on Synopsys DesignWare core.
> There are two Universal PHY (UPHY) blocks with each supporting 12(HSIO:
> Hisg Speed IO) and 8(NVHS: NVIDIA High Speed) lanes respectively.
> Controllers:0~4 use UPHY lanes from HSIO brick whereas Controller:5 uses
> UPHY lanes from NVHS brick. Lane mapping in HSIO UPHY brick to each PCIe
> controller (0~4) is controlled in XBAR module by BPMP-FW. Since PCIe
> core has PIPE interface, a glue module called PIPE-to-UPHY (P2U) is used
> to connect each UPHY lane (applicable to both HSIO and NVHS UPHY bricks)
> to PCIe controller
> This patch series
> - Adds support for P2U PHY driver
> - Adds support for PCIe host controller
> - Adds device tree nodes each PCIe controllers
> - Enables nodes applicable to p2972-0000 platform
> - Adds helper APIs in Designware core driver to get capability regs offset
> - Adds defines for new feature registers of PCIe spec revision 4
> - Makes changes in DesignWare core driver to get Tegra194 PCIe working
>
> Testing done on P2972-0000 platform
> - Able to get PCIe link up with on-board Marvel eSATA controller
> - Able to get PCIe link up with NVMe cards connected to M.2 Key-M slot
> - Able to do data transfers with both SATA drives and NVMe cards
> - Able to perform suspend-resume sequence
Do you happen to have a patch for P2972-0000 PCI support? I don't see it
in this series.
Thierry
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next prev parent reply other threads:[~2019-08-12 10:25 UTC|newest]
Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-09 4:45 [PATCH V15 00/13] PCI: tegra: Add Tegra194 PCIe support Vidya Sagar
2019-08-09 4:45 ` Vidya Sagar
2019-08-09 4:45 ` Vidya Sagar
2019-08-09 4:45 ` [PATCH V15 01/13] PCI: Add #defines for some of PCIe spec r4.0 features Vidya Sagar
2019-08-09 4:45 ` Vidya Sagar
2019-08-09 4:45 ` Vidya Sagar
2019-08-09 4:45 ` [PATCH V15 02/13] PCI: Disable MSI for Tegra root ports Vidya Sagar
2019-08-09 4:45 ` Vidya Sagar
2019-08-09 4:45 ` Vidya Sagar
2019-08-09 4:45 ` [PATCH V15 03/13] PCI: dwc: Perform dbi regs write lock towards the end Vidya Sagar
2019-08-09 4:45 ` Vidya Sagar
2019-08-09 4:45 ` Vidya Sagar
2019-08-09 4:46 ` [PATCH V15 04/13] PCI: dwc: Move config space capability search API Vidya Sagar
2019-08-09 4:46 ` Vidya Sagar
2019-08-09 4:46 ` Vidya Sagar
2019-08-09 4:46 ` [PATCH V15 05/13] PCI: dwc: Add ext " Vidya Sagar
2019-08-09 4:46 ` Vidya Sagar
2019-08-09 4:46 ` Vidya Sagar
2019-08-09 4:46 ` [PATCH V15 06/13] PCI: dwc: Export dw_pcie_wait_for_link() API Vidya Sagar
2019-08-09 4:46 ` Vidya Sagar
2019-08-09 4:46 ` Vidya Sagar
2019-08-09 4:46 ` [PATCH V15 07/13] dt-bindings: PCI: designware: Add binding for CDM register check Vidya Sagar
2019-08-09 4:46 ` Vidya Sagar
2019-08-09 4:46 ` Vidya Sagar
2019-08-09 4:46 ` [PATCH V15 08/13] PCI: dwc: Add support to enable " Vidya Sagar
2019-08-09 4:46 ` Vidya Sagar
2019-08-09 4:46 ` Vidya Sagar
2019-08-09 4:46 ` [PATCH V15 09/13] dt-bindings: Add PCIe supports-clkreq property Vidya Sagar
2019-08-09 4:46 ` Vidya Sagar
2019-08-09 4:46 ` Vidya Sagar
2019-08-09 4:46 ` [PATCH V15 10/13] dt-bindings: PCI: tegra: Add device tree support for Tegra194 Vidya Sagar
2019-08-09 4:46 ` Vidya Sagar
2019-08-09 4:46 ` Vidya Sagar
2019-08-09 4:46 ` [PATCH V15 11/13] dt-bindings: PHY: P2U: Add Tegra194 P2U block Vidya Sagar
2019-08-09 4:46 ` Vidya Sagar
2019-08-09 4:46 ` Vidya Sagar
2019-08-09 4:46 ` [PATCH V15 12/13] phy: tegra: Add PCIe PIPE2UPHY support Vidya Sagar
2019-08-09 4:46 ` Vidya Sagar
2019-08-09 4:46 ` Vidya Sagar
2019-08-12 10:23 ` Thierry Reding
2019-08-12 10:23 ` Thierry Reding
2019-08-09 4:46 ` [PATCH V15 13/13] PCI: tegra: Add Tegra194 PCIe support Vidya Sagar
2019-08-09 4:46 ` Vidya Sagar
2019-08-09 4:46 ` Vidya Sagar
2019-08-13 10:57 ` Lorenzo Pieralisi
2019-08-13 10:57 ` Lorenzo Pieralisi
2019-08-13 11:36 ` Vidya Sagar
2019-08-13 11:36 ` Vidya Sagar
2019-08-13 11:36 ` Vidya Sagar
2019-08-12 10:25 ` Thierry Reding [this message]
2019-08-12 10:25 ` [PATCH V15 00/13] " Thierry Reding
2019-08-12 10:29 ` Vidya Sagar
2019-08-12 10:29 ` Vidya Sagar
2019-08-12 10:29 ` Vidya Sagar
2019-08-12 10:34 ` Thierry Reding
2019-08-12 10:34 ` Thierry Reding
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