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From: Animesh Manna <animesh.manna@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Michel Thierry <michel.thierry@intel.com>,
	Jani Nikula <jani.nikula@intel.com>
Subject: [PATCH v2 02/15] drm/i915/dsb: DSB context creation.
Date: Wed, 21 Aug 2019 12:02:22 +0530	[thread overview]
Message-ID: <20190821063236.19705-3-animesh.manna@intel.com> (raw)
In-Reply-To: <20190821063236.19705-1-animesh.manna@intel.com>

The function will internally get the gem buffer from global GTT
which is mapped in cpu domain to feed the data + opcode for DSB engine.

Cc: Imre Deak <imre.deak@intel.com>
Cc: Michel Thierry <michel.thierry@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/Makefile                 |  1 +
 .../drm/i915/display/intel_display_types.h    |  4 ++
 drivers/gpu/drm/i915/display/intel_dsb.c      | 66 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_dsb.h      | 31 +++++++++
 drivers/gpu/drm/i915/i915_drv.h               |  1 +
 5 files changed, 103 insertions(+)
 create mode 100644 drivers/gpu/drm/i915/display/intel_dsb.c
 create mode 100644 drivers/gpu/drm/i915/display/intel_dsb.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 45add812048b..5232b2607822 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -171,6 +171,7 @@ i915-y += \
 	display/intel_display_power.o \
 	display/intel_dpio_phy.o \
 	display/intel_dpll_mgr.o \
+	display/intel_dsb.o \
 	display/intel_fbc.o \
 	display/intel_fifo_underrun.o \
 	display/intel_frontbuffer.o \
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 449abaea619f..e62450a72dc2 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1026,6 +1026,10 @@ struct intel_crtc {
 
 	/* scalers available on this crtc */
 	int num_scalers;
+
+	/* per pipe DSB related info */
+	struct intel_dsb dsb[MAX_DSB_PER_PIPE];
+	int dsb_in_use;
 };
 
 struct intel_plane {
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
new file mode 100644
index 000000000000..6cde3af30643
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -0,0 +1,66 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2019 Intel Corporation
+ *
+ */
+
+#include "../i915_drv.h"
+#include "intel_display_types.h"
+
+#define DSB_BUF_SIZE    (2 * PAGE_SIZE)
+
+struct intel_dsb *
+intel_dsb_get(struct intel_crtc *crtc)
+{
+	struct drm_device *dev = crtc->base.dev;
+	struct drm_i915_private *i915 = to_i915(dev);
+	struct drm_i915_gem_object *obj;
+	struct i915_vma *vma;
+	struct intel_dsb *dsb;
+	intel_wakeref_t wakeref;
+	int i;
+
+	WARN_ON(crtc->dsb_in_use >= MAX_DSB_PER_PIPE);
+
+	for (i = 0; i < MAX_DSB_PER_PIPE; i++) {
+		if (!crtc->dsb[i].cmd_buf) {
+			dsb = &crtc->dsb[i];
+			dsb->id = i;
+		}
+	}
+
+	dsb = &crtc->dsb[crtc->dsb_in_use];
+	dsb->crtc = crtc;
+	if (!HAS_DSB(i915))
+		return dsb;
+
+	wakeref = intel_runtime_pm_get(&i915->runtime_pm);
+	mutex_lock(&i915->drm.struct_mutex);
+
+	obj = i915_gem_object_create_shmem(i915, DSB_BUF_SIZE);
+	if (IS_ERR(obj))
+		goto err;
+
+	vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE);
+	if (IS_ERR(vma)) {
+		DRM_DEBUG_KMS("Vma creation failed.\n");
+		i915_gem_object_put(obj);
+		goto err;
+	}
+
+	dsb->cmd_buf = i915_gem_object_pin_map(vma->obj, I915_MAP_WC);
+	if (IS_ERR(dsb->cmd_buf)) {
+		DRM_DEBUG_KMS("Command buffer creation failed.\n");
+		dsb->cmd_buf = NULL;
+		goto err;
+	}
+	crtc->dsb_in_use++;
+	dsb->cmd_buf_head = (uintptr_t)i915_ggtt_offset(vma);
+	dsb->vma = vma;
+
+	memset(dsb->cmd_buf, 0, DSB_BUF_SIZE);
+err:
+	mutex_unlock(&i915->drm.struct_mutex);
+	intel_runtime_pm_put(&i915->runtime_pm, wakeref);
+	return dsb;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h b/drivers/gpu/drm/i915/display/intel_dsb.h
new file mode 100644
index 000000000000..50a2a6590a71
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_dsb.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2019 Intel Corporation
+ */
+
+#ifndef _INTEL_DSB_H
+#define _INTEL_DSB_H
+
+struct intel_crtc;
+struct i915_vma;
+
+enum dsb_id {
+	INVALID_DSB = -1,
+	DSB1,
+	DSB2,
+	DSB3,
+	MAX_DSB_PER_PIPE
+};
+
+struct intel_dsb {
+	struct intel_crtc *crtc;
+	enum dsb_id id;
+	u32 *cmd_buf;
+	u32 cmd_buf_head;
+	struct i915_vma *vma;
+};
+
+struct intel_dsb *
+intel_dsb_get(struct intel_crtc *crtc);
+
+#endif
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9e03c162a5f8..643fd6d6fd73 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -67,6 +67,7 @@
 #include "display/intel_display.h"
 #include "display/intel_display_power.h"
 #include "display/intel_dpll_mgr.h"
+#include "display/intel_dsb.h"
 #include "display/intel_frontbuffer.h"
 #include "display/intel_gmbus.h"
 #include "display/intel_opregion.h"
-- 
2.22.0

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  parent reply	other threads:[~2019-08-21  6:40 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-21  6:32 [PATCH v2 00/15] DSB enablement Animesh Manna
2019-08-21  6:32 ` [PATCH v2 01/15] drm/i915/dsb: feature flag added for display state buffer Animesh Manna
2019-08-21  6:32 ` Animesh Manna [this message]
2019-08-21 18:11   ` [PATCH v2 02/15] drm/i915/dsb: DSB context creation Chris Wilson
2019-08-22 12:05     ` Animesh Manna
2019-08-22 12:09       ` Chris Wilson
2019-10-17  8:35         ` Tvrtko Ursulin
2019-10-17 12:52           ` Animesh Manna
2019-10-17 13:09             ` Tvrtko Ursulin
2019-10-17 13:53               ` Animesh Manna
2019-10-17 14:38                 ` Tvrtko Ursulin
2019-10-21 10:11                   ` Animesh Manna
2019-10-21 10:18                     ` Chris Wilson
2019-08-21  6:32 ` [PATCH v2 03/15] drm/i915/dsb: single register write function for DSB Animesh Manna
2019-08-21  6:32 ` [PATCH v2 04/15] drm/i915/dsb: Added enum for reg write capability Animesh Manna
2019-08-22 12:57   ` Jani Nikula
2019-08-21  6:32 ` [PATCH v2 05/15] drm/i915/dsb: Indexed register write function for DSB Animesh Manna
2019-08-21 18:27   ` Chris Wilson
2019-08-22 12:06     ` Animesh Manna
2019-08-21  6:32 ` [PATCH v2 06/15] drm/i915/dsb: Update i915_write to call dsb-write Animesh Manna
2019-08-21 18:29   ` Chris Wilson
2019-08-22 13:11     ` Jani Nikula
2019-08-21  6:32 ` [PATCH v2 07/15] drm/i915/dsb: Register definition of DSB registers Animesh Manna
2019-08-21  6:32 ` [PATCH v2 08/15] drm/i915/dsb: Check DSB engine status Animesh Manna
2019-08-21  6:32 ` [PATCH v2 09/15] drm/i915/dsb: functions to enable/disable DSB engine Animesh Manna
2019-08-21  6:32 ` [PATCH v2 10/15] drm/i915/dsb: function to trigger workload execution of DSB Animesh Manna
2019-08-21 18:43   ` Chris Wilson
2019-08-22 12:07     ` Animesh Manna
2019-08-21  6:32 ` [PATCH v2 11/15] drm/i915/dsb: function to destroy DSB context Animesh Manna
2019-08-21 18:45   ` Chris Wilson
2019-08-21  6:32 ` [PATCH v2 12/15] drm/i915/dsb: Early prepare of dsb context Animesh Manna
2019-08-21  6:32 ` [PATCH v2 13/15] drm/i915/dsb: Cleanup of DSB context Animesh Manna
2019-08-21  6:32 ` [PATCH v2 14/15] drm/i915/dsb: Documentation for DSB Animesh Manna
2019-08-21  6:32 ` [PATCH v2 15/15] drm/i915/dsb: Enable gamma lut programming using DSB Animesh Manna
2019-08-22 13:23   ` Jani Nikula
2019-08-22 14:45     ` Animesh Manna
2019-08-21  7:11 ` ✗ Fi.CI.CHECKPATCH: warning for DSB enablement. (rev2) Patchwork
2019-08-21  7:12 ` ✗ Fi.CI.SPARSE: " Patchwork
2019-08-21  7:32 ` ✓ Fi.CI.BAT: success " Patchwork
2019-08-21 18:46 ` ✗ Fi.CI.IGT: failure " Patchwork

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