From: <Tudor.Ambarus@microchip.com> To: <marek.vasut@gmail.com>, <miquel.raynal@bootlin.com>, <richard@nod.at>, <vigneshr@ti.com>, <joel@jms.id.au>, <andrew@aj.id.au>, <matthias.bgg@gmail.com>, <vz@mleia.com>, <boris.brezillon@collabora.com>, <linux-mtd@lists.infradead.org>, <linux-arm-kernel@lists.infradead.org> Cc: Tudor.Ambarus@microchip.com Subject: [PATCH 10/13] mtd: spi-nor: Rework spi_nor_read/write_sr2() Date: Wed, 11 Sep 2019 09:41:17 +0000 [thread overview] Message-ID: <20190911094031.17615-11-tudor.ambarus@microchip.com> (raw) In-Reply-To: <20190911094031.17615-1-tudor.ambarus@microchip.com> From: Tudor Ambarus <tudor.ambarus@microchip.com> Move the methods up in the file, where the other Register operations reside. The error is reported inside each SR2 function, to spare the callers of duplicating code. Constify sr2 in spi_nor_write_sr2(). Do the spi_nor_write_enable() and spi_nor_wait_till_ready() inside spi_nor_write_sr2(), as the spi_nor_write_sr() does. While modyfing sr2_bit7_quad_enable(), add a new line for better code readability. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> --- drivers/mtd/spi-nor/spi-nor.c | 118 ++++++++++++++++++++++++++---------------- 1 file changed, 74 insertions(+), 44 deletions(-) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index a903717788f4..b720c0003b27 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -731,6 +731,74 @@ static int spi_nor_write_sr(struct spi_nor *nor, const u8 *sr, size_t len) return ret; } +/** + * spi_nor_write_sr2() - Write the Status Register 2 using the + * SPINOR_OP_WRSR2 (3eh) command. + * @nor: pointer to 'struct spi_nor'. + * @sr2: buffer to write to the Status Register. + * + * Return: 0 on success, -errno otherwise. + */ +static int spi_nor_write_sr2(struct spi_nor *nor, const u8 *sr2) +{ + int ret; + + ret = spi_nor_write_enable(nor); + if (ret) + return ret; + + if (nor->spimem) { + struct spi_mem_op op = + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRSR2, 1), + SPI_MEM_OP_NO_ADDR, + SPI_MEM_OP_NO_DUMMY, + SPI_MEM_OP_DATA_OUT(1, sr2, 1)); + + ret = spi_mem_exec_op(nor->spimem, &op); + } else { + ret = nor->controller_ops->write_reg(nor, SPINOR_OP_WRSR2, + sr2, 1); + } + + if (ret) + dev_err(nor->dev, "error while writing Status Register 2\n"); + + ret = spi_nor_wait_till_ready(nor); + + return ret; +} + +/** + * spi_nor_read_sr2() - Read the Status Register 2 using the + * SPINOR_OP_RDSR2 (3fh) command. + * @nor: pointer to 'struct spi_nor' + * @sr2: buffer where the value of the Status Register will be written. + * + * Return: 0 on success, -errno otherwise. + */ +static int spi_nor_read_sr2(struct spi_nor *nor, u8 *sr2) +{ + int ret; + + if (nor->spimem) { + struct spi_mem_op op = + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDSR2, 1), + SPI_MEM_OP_NO_ADDR, + SPI_MEM_OP_NO_DUMMY, + SPI_MEM_OP_DATA_IN(1, sr2, 1)); + + ret = spi_mem_exec_op(nor->spimem, &op); + } else { + ret = nor->controller_ops->read_reg(nor, SPINOR_OP_RDSR2, + sr2, 1); + } + + if (ret) + dev_err(nor->dev, "error while reading Status Register 2\n"); + + return ret; +} + static struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd) { return mtd->priv; @@ -1889,36 +1957,6 @@ static int spansion_read_cr_quad_enable(struct spi_nor *nor) return 0; } -static int spi_nor_write_sr2(struct spi_nor *nor, u8 *sr2) -{ - if (nor->spimem) { - struct spi_mem_op op = - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRSR2, 1), - SPI_MEM_OP_NO_ADDR, - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_DATA_OUT(1, sr2, 1)); - - return spi_mem_exec_op(nor->spimem, &op); - } - - return nor->controller_ops->write_reg(nor, SPINOR_OP_WRSR2, sr2, 1); -} - -static int spi_nor_read_sr2(struct spi_nor *nor, u8 *sr2) -{ - if (nor->spimem) { - struct spi_mem_op op = - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDSR2, 1), - SPI_MEM_OP_NO_ADDR, - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_DATA_IN(1, sr2, 1)); - - return spi_mem_exec_op(nor->spimem, &op); - } - - return nor->controller_ops->read_reg(nor, SPINOR_OP_RDSR2, sr2, 1); -} - /** * sr2_bit7_quad_enable() - set QE bit in Status Register 2. * @nor: pointer to a 'struct spi_nor' @@ -1940,31 +1978,23 @@ static int sr2_bit7_quad_enable(struct spi_nor *nor) ret = spi_nor_read_sr2(nor, sr2); if (ret) return ret; + if (*sr2 & SR2_QUAD_EN_BIT7) return 0; /* Update the Quad Enable bit. */ *sr2 |= SR2_QUAD_EN_BIT7; - ret = spi_nor_write_enable(nor); - if (ret) - return ret; - ret = spi_nor_write_sr2(nor, sr2); - if (ret < 0) { - dev_err(nor->dev, "error while writing status register 2\n"); - return -EINVAL; - } - - ret = spi_nor_wait_till_ready(nor); - if (ret < 0) { - dev_err(nor->dev, "timeout while writing status register 2\n"); + if (ret) return ret; - } /* Read back and check it. */ ret = spi_nor_read_sr2(nor, sr2); - if (!(ret > 0 && (*sr2 & SR2_QUAD_EN_BIT7))) { + if (ret) + return ret; + + if (!(*sr2 & SR2_QUAD_EN_BIT7)) { dev_err(nor->dev, "SR2 Quad bit not set\n"); return -EINVAL; } -- 2.9.5 ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/
WARNING: multiple messages have this Message-ID (diff)
From: <Tudor.Ambarus@microchip.com> To: <marek.vasut@gmail.com>, <miquel.raynal@bootlin.com>, <richard@nod.at>, <vigneshr@ti.com>, <joel@jms.id.au>, <andrew@aj.id.au>, <matthias.bgg@gmail.com>, <vz@mleia.com>, <boris.brezillon@collabora.com>, <linux-mtd@lists.infradead.org>, <linux-arm-kernel@lists.infradead.org> Cc: Tudor.Ambarus@microchip.com Subject: [PATCH 10/13] mtd: spi-nor: Rework spi_nor_read/write_sr2() Date: Wed, 11 Sep 2019 09:41:17 +0000 [thread overview] Message-ID: <20190911094031.17615-11-tudor.ambarus@microchip.com> (raw) In-Reply-To: <20190911094031.17615-1-tudor.ambarus@microchip.com> From: Tudor Ambarus <tudor.ambarus@microchip.com> Move the methods up in the file, where the other Register operations reside. The error is reported inside each SR2 function, to spare the callers of duplicating code. Constify sr2 in spi_nor_write_sr2(). Do the spi_nor_write_enable() and spi_nor_wait_till_ready() inside spi_nor_write_sr2(), as the spi_nor_write_sr() does. While modyfing sr2_bit7_quad_enable(), add a new line for better code readability. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> --- drivers/mtd/spi-nor/spi-nor.c | 118 ++++++++++++++++++++++++++---------------- 1 file changed, 74 insertions(+), 44 deletions(-) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index a903717788f4..b720c0003b27 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -731,6 +731,74 @@ static int spi_nor_write_sr(struct spi_nor *nor, const u8 *sr, size_t len) return ret; } +/** + * spi_nor_write_sr2() - Write the Status Register 2 using the + * SPINOR_OP_WRSR2 (3eh) command. + * @nor: pointer to 'struct spi_nor'. + * @sr2: buffer to write to the Status Register. + * + * Return: 0 on success, -errno otherwise. + */ +static int spi_nor_write_sr2(struct spi_nor *nor, const u8 *sr2) +{ + int ret; + + ret = spi_nor_write_enable(nor); + if (ret) + return ret; + + if (nor->spimem) { + struct spi_mem_op op = + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRSR2, 1), + SPI_MEM_OP_NO_ADDR, + SPI_MEM_OP_NO_DUMMY, + SPI_MEM_OP_DATA_OUT(1, sr2, 1)); + + ret = spi_mem_exec_op(nor->spimem, &op); + } else { + ret = nor->controller_ops->write_reg(nor, SPINOR_OP_WRSR2, + sr2, 1); + } + + if (ret) + dev_err(nor->dev, "error while writing Status Register 2\n"); + + ret = spi_nor_wait_till_ready(nor); + + return ret; +} + +/** + * spi_nor_read_sr2() - Read the Status Register 2 using the + * SPINOR_OP_RDSR2 (3fh) command. + * @nor: pointer to 'struct spi_nor' + * @sr2: buffer where the value of the Status Register will be written. + * + * Return: 0 on success, -errno otherwise. + */ +static int spi_nor_read_sr2(struct spi_nor *nor, u8 *sr2) +{ + int ret; + + if (nor->spimem) { + struct spi_mem_op op = + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDSR2, 1), + SPI_MEM_OP_NO_ADDR, + SPI_MEM_OP_NO_DUMMY, + SPI_MEM_OP_DATA_IN(1, sr2, 1)); + + ret = spi_mem_exec_op(nor->spimem, &op); + } else { + ret = nor->controller_ops->read_reg(nor, SPINOR_OP_RDSR2, + sr2, 1); + } + + if (ret) + dev_err(nor->dev, "error while reading Status Register 2\n"); + + return ret; +} + static struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd) { return mtd->priv; @@ -1889,36 +1957,6 @@ static int spansion_read_cr_quad_enable(struct spi_nor *nor) return 0; } -static int spi_nor_write_sr2(struct spi_nor *nor, u8 *sr2) -{ - if (nor->spimem) { - struct spi_mem_op op = - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRSR2, 1), - SPI_MEM_OP_NO_ADDR, - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_DATA_OUT(1, sr2, 1)); - - return spi_mem_exec_op(nor->spimem, &op); - } - - return nor->controller_ops->write_reg(nor, SPINOR_OP_WRSR2, sr2, 1); -} - -static int spi_nor_read_sr2(struct spi_nor *nor, u8 *sr2) -{ - if (nor->spimem) { - struct spi_mem_op op = - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDSR2, 1), - SPI_MEM_OP_NO_ADDR, - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_DATA_IN(1, sr2, 1)); - - return spi_mem_exec_op(nor->spimem, &op); - } - - return nor->controller_ops->read_reg(nor, SPINOR_OP_RDSR2, sr2, 1); -} - /** * sr2_bit7_quad_enable() - set QE bit in Status Register 2. * @nor: pointer to a 'struct spi_nor' @@ -1940,31 +1978,23 @@ static int sr2_bit7_quad_enable(struct spi_nor *nor) ret = spi_nor_read_sr2(nor, sr2); if (ret) return ret; + if (*sr2 & SR2_QUAD_EN_BIT7) return 0; /* Update the Quad Enable bit. */ *sr2 |= SR2_QUAD_EN_BIT7; - ret = spi_nor_write_enable(nor); - if (ret) - return ret; - ret = spi_nor_write_sr2(nor, sr2); - if (ret < 0) { - dev_err(nor->dev, "error while writing status register 2\n"); - return -EINVAL; - } - - ret = spi_nor_wait_till_ready(nor); - if (ret < 0) { - dev_err(nor->dev, "timeout while writing status register 2\n"); + if (ret) return ret; - } /* Read back and check it. */ ret = spi_nor_read_sr2(nor, sr2); - if (!(ret > 0 && (*sr2 & SR2_QUAD_EN_BIT7))) { + if (ret) + return ret; + + if (!(*sr2 & SR2_QUAD_EN_BIT7)) { dev_err(nor->dev, "SR2 Quad bit not set\n"); return -EINVAL; } -- 2.9.5 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2019-09-11 9:47 UTC|newest] Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-09-11 9:40 [PATCH 00/13] mtd: spi-nor: Clean Flash Register operations Tudor.Ambarus 2019-09-11 9:40 ` Tudor.Ambarus 2019-09-11 9:40 ` [PATCH 01/13] mtd: spi-nor: hisi-sfc: Drop nor->erase NULL asignment Tudor.Ambarus 2019-09-11 9:40 ` Tudor.Ambarus 2019-09-11 9:40 ` [PATCH 02/13] mtd: spi-nor: Introduce 'struct spi_nor_controller_ops' Tudor.Ambarus 2019-09-11 9:40 ` Tudor.Ambarus 2019-09-11 9:40 ` [PATCH 03/13] mtd: spi-nor: cadence-quadspi: Fix cqspi_command_read() definition Tudor.Ambarus 2019-09-11 9:40 ` Tudor.Ambarus 2019-09-11 9:40 ` [PATCH 04/13] mtd: spi-nor: Rename nor->params to nor->flash Tudor.Ambarus 2019-09-11 9:40 ` Tudor.Ambarus 2019-09-11 9:41 ` [PATCH 05/13] mtd: spi-nor: Rework read_sr() Tudor.Ambarus 2019-09-11 9:41 ` Tudor.Ambarus 2019-09-11 9:41 ` [PATCH 06/13] mtd: spi-nor: Rework read_fsr() Tudor.Ambarus 2019-09-11 9:41 ` Tudor.Ambarus 2019-09-11 9:41 ` [PATCH 07/13] mtd: spi-nor: Rework read_cr() Tudor.Ambarus 2019-09-11 9:41 ` Tudor.Ambarus 2019-09-11 9:41 ` [PATCH 08/13] mtd: spi-nor: Rework write_enable/disable() Tudor.Ambarus 2019-09-11 9:41 ` Tudor.Ambarus 2019-09-11 9:41 ` [PATCH 09/13] mtd: spi-nor: Rework write_sr() Tudor.Ambarus 2019-09-11 9:41 ` Tudor.Ambarus 2019-09-11 9:41 ` Tudor.Ambarus [this message] 2019-09-11 9:41 ` [PATCH 10/13] mtd: spi-nor: Rework spi_nor_read/write_sr2() Tudor.Ambarus 2019-09-11 9:41 ` [PATCH 11/13] mtd: spi-nor: Report error in spi_nor_xread_sr() Tudor.Ambarus 2019-09-11 9:41 ` Tudor.Ambarus 2019-09-11 9:41 ` [PATCH 12/13] mtd: spi-nor: Void return type for spi_nor_clear_sr/fsr() Tudor.Ambarus 2019-09-11 9:41 ` Tudor.Ambarus 2019-09-11 9:41 ` [PATCH 13/13] mtd: spi-nor: Drop duplicated new line Tudor.Ambarus 2019-09-11 9:41 ` Tudor.Ambarus
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