From: Palmer Dabbelt <palmer@sifive.com> To: Peter Maydell <peter.maydell@linaro.org> Cc: Alistair Francis <alistair.francis@wdc.com>, Bin Meng <bmeng.cn@gmail.com>, qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Palmer Dabbelt <palmer@sifive.com> Subject: [Qemu-devel] [PULL 40/48] riscv: sifive: Implement a model for SiFive FU540 OTP Date: Wed, 18 Sep 2019 07:56:32 -0700 [thread overview] Message-ID: <20190918145640.17349-41-palmer@sifive.com> (raw) In-Reply-To: <20190918145640.17349-1-palmer@sifive.com> From: Bin Meng <bmeng.cn@gmail.com> This implements a simple model for SiFive FU540 OTP (One-Time Programmable) Memory interface, primarily for reading out the stored serial number from the first 1 KiB of the 16 KiB OTP memory reserved by SiFive for internal use. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> --- hw/riscv/Makefile.objs | 1 + hw/riscv/sifive_u_otp.c | 191 ++++++++++++++++++++++++++++++++ include/hw/riscv/sifive_u_otp.h | 80 +++++++++++++ 3 files changed, 272 insertions(+) create mode 100644 hw/riscv/sifive_u_otp.c create mode 100644 include/hw/riscv/sifive_u_otp.h diff --git a/hw/riscv/Makefile.objs b/hw/riscv/Makefile.objs index b95bbd51e2..fc3c6dd7c8 100644 --- a/hw/riscv/Makefile.objs +++ b/hw/riscv/Makefile.objs @@ -8,6 +8,7 @@ obj-$(CONFIG_SIFIVE) += sifive_gpio.o obj-$(CONFIG_SIFIVE) += sifive_plic.o obj-$(CONFIG_SIFIVE) += sifive_test.o obj-$(CONFIG_SIFIVE_U) += sifive_u.o +obj-$(CONFIG_SIFIVE_U) += sifive_u_otp.o obj-$(CONFIG_SIFIVE_U) += sifive_u_prci.o obj-$(CONFIG_SIFIVE) += sifive_uart.o obj-$(CONFIG_SPIKE) += spike.o diff --git a/hw/riscv/sifive_u_otp.c b/hw/riscv/sifive_u_otp.c new file mode 100644 index 0000000000..ea0eee5678 --- /dev/null +++ b/hw/riscv/sifive_u_otp.c @@ -0,0 +1,191 @@ +/* + * QEMU SiFive U OTP (One-Time Programmable) Memory interface + * + * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com> + * + * Simple model of the OTP to emulate register reads made by the SDK BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include "qemu/osdep.h" +#include "hw/qdev-properties.h" +#include "hw/sysbus.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "hw/riscv/sifive_u_otp.h" + +static uint64_t sifive_u_otp_read(void *opaque, hwaddr addr, unsigned int size) +{ + SiFiveUOTPState *s = opaque; + + switch (addr) { + case SIFIVE_U_OTP_PA: + return s->pa; + case SIFIVE_U_OTP_PAIO: + return s->paio; + case SIFIVE_U_OTP_PAS: + return s->pas; + case SIFIVE_U_OTP_PCE: + return s->pce; + case SIFIVE_U_OTP_PCLK: + return s->pclk; + case SIFIVE_U_OTP_PDIN: + return s->pdin; + case SIFIVE_U_OTP_PDOUT: + if ((s->pce & SIFIVE_U_OTP_PCE_EN) && + (s->pdstb & SIFIVE_U_OTP_PDSTB_EN) && + (s->ptrim & SIFIVE_U_OTP_PTRIM_EN)) { + return s->fuse[s->pa & SIFIVE_U_OTP_PA_MASK]; + } else { + return 0xff; + } + case SIFIVE_U_OTP_PDSTB: + return s->pdstb; + case SIFIVE_U_OTP_PPROG: + return s->pprog; + case SIFIVE_U_OTP_PTC: + return s->ptc; + case SIFIVE_U_OTP_PTM: + return s->ptm; + case SIFIVE_U_OTP_PTM_REP: + return s->ptm_rep; + case SIFIVE_U_OTP_PTR: + return s->ptr; + case SIFIVE_U_OTP_PTRIM: + return s->ptrim; + case SIFIVE_U_OTP_PWE: + return s->pwe; + } + + qemu_log_mask(LOG_GUEST_ERROR, "%s: read: addr=0x%" HWADDR_PRIx "\n", + __func__, addr); + return 0; +} + +static void sifive_u_otp_write(void *opaque, hwaddr addr, + uint64_t val64, unsigned int size) +{ + SiFiveUOTPState *s = opaque; + uint32_t val32 = (uint32_t)val64; + + switch (addr) { + case SIFIVE_U_OTP_PA: + s->pa = val32 & SIFIVE_U_OTP_PA_MASK; + break; + case SIFIVE_U_OTP_PAIO: + s->paio = val32; + break; + case SIFIVE_U_OTP_PAS: + s->pas = val32; + break; + case SIFIVE_U_OTP_PCE: + s->pce = val32; + break; + case SIFIVE_U_OTP_PCLK: + s->pclk = val32; + break; + case SIFIVE_U_OTP_PDIN: + s->pdin = val32; + break; + case SIFIVE_U_OTP_PDOUT: + /* read-only */ + break; + case SIFIVE_U_OTP_PDSTB: + s->pdstb = val32; + break; + case SIFIVE_U_OTP_PPROG: + s->pprog = val32; + break; + case SIFIVE_U_OTP_PTC: + s->ptc = val32; + break; + case SIFIVE_U_OTP_PTM: + s->ptm = val32; + break; + case SIFIVE_U_OTP_PTM_REP: + s->ptm_rep = val32; + break; + case SIFIVE_U_OTP_PTR: + s->ptr = val32; + break; + case SIFIVE_U_OTP_PTRIM: + s->ptrim = val32; + break; + case SIFIVE_U_OTP_PWE: + s->pwe = val32; + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write: addr=0x%" HWADDR_PRIx + " v=0x%x\n", __func__, addr, val32); + } +} + +static const MemoryRegionOps sifive_u_otp_ops = { + .read = sifive_u_otp_read, + .write = sifive_u_otp_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4 + } +}; + +static Property sifive_u_otp_properties[] = { + DEFINE_PROP_UINT32("serial", SiFiveUOTPState, serial, 0), + DEFINE_PROP_END_OF_LIST(), +}; + +static void sifive_u_otp_realize(DeviceState *dev, Error **errp) +{ + SiFiveUOTPState *s = SIFIVE_U_OTP(dev); + + memory_region_init_io(&s->mmio, OBJECT(dev), &sifive_u_otp_ops, s, + TYPE_SIFIVE_U_OTP, SIFIVE_U_OTP_REG_SIZE); + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio); +} + +static void sifive_u_otp_reset(DeviceState *dev) +{ + SiFiveUOTPState *s = SIFIVE_U_OTP(dev); + + /* Initialize all fuses' initial value to 0xFFs */ + memset(s->fuse, 0xff, sizeof(s->fuse)); + + /* Make a valid content of serial number */ + s->fuse[SIFIVE_U_OTP_SERIAL_ADDR] = s->serial; + s->fuse[SIFIVE_U_OTP_SERIAL_ADDR + 1] = ~(s->serial); +} + +static void sifive_u_otp_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->props = sifive_u_otp_properties; + dc->realize = sifive_u_otp_realize; + dc->reset = sifive_u_otp_reset; +} + +static const TypeInfo sifive_u_otp_info = { + .name = TYPE_SIFIVE_U_OTP, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(SiFiveUOTPState), + .class_init = sifive_u_otp_class_init, +}; + +static void sifive_u_otp_register_types(void) +{ + type_register_static(&sifive_u_otp_info); +} + +type_init(sifive_u_otp_register_types) diff --git a/include/hw/riscv/sifive_u_otp.h b/include/hw/riscv/sifive_u_otp.h new file mode 100644 index 0000000000..639297564a --- /dev/null +++ b/include/hw/riscv/sifive_u_otp.h @@ -0,0 +1,80 @@ +/* + * QEMU SiFive U OTP (One-Time Programmable) Memory interface + * + * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef HW_SIFIVE_U_OTP_H +#define HW_SIFIVE_U_OTP_H + +#define SIFIVE_U_OTP_PA 0x00 +#define SIFIVE_U_OTP_PAIO 0x04 +#define SIFIVE_U_OTP_PAS 0x08 +#define SIFIVE_U_OTP_PCE 0x0C +#define SIFIVE_U_OTP_PCLK 0x10 +#define SIFIVE_U_OTP_PDIN 0x14 +#define SIFIVE_U_OTP_PDOUT 0x18 +#define SIFIVE_U_OTP_PDSTB 0x1C +#define SIFIVE_U_OTP_PPROG 0x20 +#define SIFIVE_U_OTP_PTC 0x24 +#define SIFIVE_U_OTP_PTM 0x28 +#define SIFIVE_U_OTP_PTM_REP 0x2C +#define SIFIVE_U_OTP_PTR 0x30 +#define SIFIVE_U_OTP_PTRIM 0x34 +#define SIFIVE_U_OTP_PWE 0x38 + +#define SIFIVE_U_OTP_PCE_EN (1 << 0) + +#define SIFIVE_U_OTP_PDSTB_EN (1 << 0) + +#define SIFIVE_U_OTP_PTRIM_EN (1 << 0) + +#define SIFIVE_U_OTP_PA_MASK 0xfff +#define SIFIVE_U_OTP_NUM_FUSES 0x1000 +#define SIFIVE_U_OTP_SERIAL_ADDR 0xfc + +#define SIFIVE_U_OTP_REG_SIZE 0x1000 + +#define TYPE_SIFIVE_U_OTP "riscv.sifive.u.otp" + +#define SIFIVE_U_OTP(obj) \ + OBJECT_CHECK(SiFiveUOTPState, (obj), TYPE_SIFIVE_U_OTP) + +typedef struct SiFiveUOTPState { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + MemoryRegion mmio; + uint32_t pa; + uint32_t paio; + uint32_t pas; + uint32_t pce; + uint32_t pclk; + uint32_t pdin; + uint32_t pdstb; + uint32_t pprog; + uint32_t ptc; + uint32_t ptm; + uint32_t ptm_rep; + uint32_t ptr; + uint32_t ptrim; + uint32_t pwe; + uint32_t fuse[SIFIVE_U_OTP_NUM_FUSES]; + /* config */ + uint32_t serial; +} SiFiveUOTPState; + +#endif /* HW_SIFIVE_U_OTP_H */ -- 2.21.0
WARNING: multiple messages have this Message-ID (diff)
From: Palmer Dabbelt <palmer@sifive.com> To: Peter Maydell <peter.maydell@linaro.org> Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Bin Meng <bmeng.cn@gmail.com>, Alistair Francis <alistair.francis@wdc.com>, Palmer Dabbelt <palmer@sifive.com> Subject: [Qemu-riscv] [PULL 40/48] riscv: sifive: Implement a model for SiFive FU540 OTP Date: Wed, 18 Sep 2019 07:56:32 -0700 [thread overview] Message-ID: <20190918145640.17349-41-palmer@sifive.com> (raw) In-Reply-To: <20190918145640.17349-1-palmer@sifive.com> From: Bin Meng <bmeng.cn@gmail.com> This implements a simple model for SiFive FU540 OTP (One-Time Programmable) Memory interface, primarily for reading out the stored serial number from the first 1 KiB of the 16 KiB OTP memory reserved by SiFive for internal use. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> --- hw/riscv/Makefile.objs | 1 + hw/riscv/sifive_u_otp.c | 191 ++++++++++++++++++++++++++++++++ include/hw/riscv/sifive_u_otp.h | 80 +++++++++++++ 3 files changed, 272 insertions(+) create mode 100644 hw/riscv/sifive_u_otp.c create mode 100644 include/hw/riscv/sifive_u_otp.h diff --git a/hw/riscv/Makefile.objs b/hw/riscv/Makefile.objs index b95bbd51e2..fc3c6dd7c8 100644 --- a/hw/riscv/Makefile.objs +++ b/hw/riscv/Makefile.objs @@ -8,6 +8,7 @@ obj-$(CONFIG_SIFIVE) += sifive_gpio.o obj-$(CONFIG_SIFIVE) += sifive_plic.o obj-$(CONFIG_SIFIVE) += sifive_test.o obj-$(CONFIG_SIFIVE_U) += sifive_u.o +obj-$(CONFIG_SIFIVE_U) += sifive_u_otp.o obj-$(CONFIG_SIFIVE_U) += sifive_u_prci.o obj-$(CONFIG_SIFIVE) += sifive_uart.o obj-$(CONFIG_SPIKE) += spike.o diff --git a/hw/riscv/sifive_u_otp.c b/hw/riscv/sifive_u_otp.c new file mode 100644 index 0000000000..ea0eee5678 --- /dev/null +++ b/hw/riscv/sifive_u_otp.c @@ -0,0 +1,191 @@ +/* + * QEMU SiFive U OTP (One-Time Programmable) Memory interface + * + * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com> + * + * Simple model of the OTP to emulate register reads made by the SDK BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include "qemu/osdep.h" +#include "hw/qdev-properties.h" +#include "hw/sysbus.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "hw/riscv/sifive_u_otp.h" + +static uint64_t sifive_u_otp_read(void *opaque, hwaddr addr, unsigned int size) +{ + SiFiveUOTPState *s = opaque; + + switch (addr) { + case SIFIVE_U_OTP_PA: + return s->pa; + case SIFIVE_U_OTP_PAIO: + return s->paio; + case SIFIVE_U_OTP_PAS: + return s->pas; + case SIFIVE_U_OTP_PCE: + return s->pce; + case SIFIVE_U_OTP_PCLK: + return s->pclk; + case SIFIVE_U_OTP_PDIN: + return s->pdin; + case SIFIVE_U_OTP_PDOUT: + if ((s->pce & SIFIVE_U_OTP_PCE_EN) && + (s->pdstb & SIFIVE_U_OTP_PDSTB_EN) && + (s->ptrim & SIFIVE_U_OTP_PTRIM_EN)) { + return s->fuse[s->pa & SIFIVE_U_OTP_PA_MASK]; + } else { + return 0xff; + } + case SIFIVE_U_OTP_PDSTB: + return s->pdstb; + case SIFIVE_U_OTP_PPROG: + return s->pprog; + case SIFIVE_U_OTP_PTC: + return s->ptc; + case SIFIVE_U_OTP_PTM: + return s->ptm; + case SIFIVE_U_OTP_PTM_REP: + return s->ptm_rep; + case SIFIVE_U_OTP_PTR: + return s->ptr; + case SIFIVE_U_OTP_PTRIM: + return s->ptrim; + case SIFIVE_U_OTP_PWE: + return s->pwe; + } + + qemu_log_mask(LOG_GUEST_ERROR, "%s: read: addr=0x%" HWADDR_PRIx "\n", + __func__, addr); + return 0; +} + +static void sifive_u_otp_write(void *opaque, hwaddr addr, + uint64_t val64, unsigned int size) +{ + SiFiveUOTPState *s = opaque; + uint32_t val32 = (uint32_t)val64; + + switch (addr) { + case SIFIVE_U_OTP_PA: + s->pa = val32 & SIFIVE_U_OTP_PA_MASK; + break; + case SIFIVE_U_OTP_PAIO: + s->paio = val32; + break; + case SIFIVE_U_OTP_PAS: + s->pas = val32; + break; + case SIFIVE_U_OTP_PCE: + s->pce = val32; + break; + case SIFIVE_U_OTP_PCLK: + s->pclk = val32; + break; + case SIFIVE_U_OTP_PDIN: + s->pdin = val32; + break; + case SIFIVE_U_OTP_PDOUT: + /* read-only */ + break; + case SIFIVE_U_OTP_PDSTB: + s->pdstb = val32; + break; + case SIFIVE_U_OTP_PPROG: + s->pprog = val32; + break; + case SIFIVE_U_OTP_PTC: + s->ptc = val32; + break; + case SIFIVE_U_OTP_PTM: + s->ptm = val32; + break; + case SIFIVE_U_OTP_PTM_REP: + s->ptm_rep = val32; + break; + case SIFIVE_U_OTP_PTR: + s->ptr = val32; + break; + case SIFIVE_U_OTP_PTRIM: + s->ptrim = val32; + break; + case SIFIVE_U_OTP_PWE: + s->pwe = val32; + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write: addr=0x%" HWADDR_PRIx + " v=0x%x\n", __func__, addr, val32); + } +} + +static const MemoryRegionOps sifive_u_otp_ops = { + .read = sifive_u_otp_read, + .write = sifive_u_otp_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4 + } +}; + +static Property sifive_u_otp_properties[] = { + DEFINE_PROP_UINT32("serial", SiFiveUOTPState, serial, 0), + DEFINE_PROP_END_OF_LIST(), +}; + +static void sifive_u_otp_realize(DeviceState *dev, Error **errp) +{ + SiFiveUOTPState *s = SIFIVE_U_OTP(dev); + + memory_region_init_io(&s->mmio, OBJECT(dev), &sifive_u_otp_ops, s, + TYPE_SIFIVE_U_OTP, SIFIVE_U_OTP_REG_SIZE); + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio); +} + +static void sifive_u_otp_reset(DeviceState *dev) +{ + SiFiveUOTPState *s = SIFIVE_U_OTP(dev); + + /* Initialize all fuses' initial value to 0xFFs */ + memset(s->fuse, 0xff, sizeof(s->fuse)); + + /* Make a valid content of serial number */ + s->fuse[SIFIVE_U_OTP_SERIAL_ADDR] = s->serial; + s->fuse[SIFIVE_U_OTP_SERIAL_ADDR + 1] = ~(s->serial); +} + +static void sifive_u_otp_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->props = sifive_u_otp_properties; + dc->realize = sifive_u_otp_realize; + dc->reset = sifive_u_otp_reset; +} + +static const TypeInfo sifive_u_otp_info = { + .name = TYPE_SIFIVE_U_OTP, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(SiFiveUOTPState), + .class_init = sifive_u_otp_class_init, +}; + +static void sifive_u_otp_register_types(void) +{ + type_register_static(&sifive_u_otp_info); +} + +type_init(sifive_u_otp_register_types) diff --git a/include/hw/riscv/sifive_u_otp.h b/include/hw/riscv/sifive_u_otp.h new file mode 100644 index 0000000000..639297564a --- /dev/null +++ b/include/hw/riscv/sifive_u_otp.h @@ -0,0 +1,80 @@ +/* + * QEMU SiFive U OTP (One-Time Programmable) Memory interface + * + * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef HW_SIFIVE_U_OTP_H +#define HW_SIFIVE_U_OTP_H + +#define SIFIVE_U_OTP_PA 0x00 +#define SIFIVE_U_OTP_PAIO 0x04 +#define SIFIVE_U_OTP_PAS 0x08 +#define SIFIVE_U_OTP_PCE 0x0C +#define SIFIVE_U_OTP_PCLK 0x10 +#define SIFIVE_U_OTP_PDIN 0x14 +#define SIFIVE_U_OTP_PDOUT 0x18 +#define SIFIVE_U_OTP_PDSTB 0x1C +#define SIFIVE_U_OTP_PPROG 0x20 +#define SIFIVE_U_OTP_PTC 0x24 +#define SIFIVE_U_OTP_PTM 0x28 +#define SIFIVE_U_OTP_PTM_REP 0x2C +#define SIFIVE_U_OTP_PTR 0x30 +#define SIFIVE_U_OTP_PTRIM 0x34 +#define SIFIVE_U_OTP_PWE 0x38 + +#define SIFIVE_U_OTP_PCE_EN (1 << 0) + +#define SIFIVE_U_OTP_PDSTB_EN (1 << 0) + +#define SIFIVE_U_OTP_PTRIM_EN (1 << 0) + +#define SIFIVE_U_OTP_PA_MASK 0xfff +#define SIFIVE_U_OTP_NUM_FUSES 0x1000 +#define SIFIVE_U_OTP_SERIAL_ADDR 0xfc + +#define SIFIVE_U_OTP_REG_SIZE 0x1000 + +#define TYPE_SIFIVE_U_OTP "riscv.sifive.u.otp" + +#define SIFIVE_U_OTP(obj) \ + OBJECT_CHECK(SiFiveUOTPState, (obj), TYPE_SIFIVE_U_OTP) + +typedef struct SiFiveUOTPState { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + MemoryRegion mmio; + uint32_t pa; + uint32_t paio; + uint32_t pas; + uint32_t pce; + uint32_t pclk; + uint32_t pdin; + uint32_t pdstb; + uint32_t pprog; + uint32_t ptc; + uint32_t ptm; + uint32_t ptm_rep; + uint32_t ptr; + uint32_t ptrim; + uint32_t pwe; + uint32_t fuse[SIFIVE_U_OTP_NUM_FUSES]; + /* config */ + uint32_t serial; +} SiFiveUOTPState; + +#endif /* HW_SIFIVE_U_OTP_H */ -- 2.21.0
next prev parent reply other threads:[~2019-09-18 16:05 UTC|newest] Thread overview: 104+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-09-18 14:55 [Qemu-devel] [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1, v3 Palmer Dabbelt 2019-09-18 14:55 ` [Qemu-riscv] " Palmer Dabbelt 2019-09-18 14:55 ` [Qemu-devel] [PULL 01/48] riscv: sifive_u: Add support for loading initrd Palmer Dabbelt 2019-09-18 14:55 ` [Qemu-riscv] " Palmer Dabbelt 2019-09-18 14:55 ` [Qemu-devel] [PULL 02/48] riscv: sivive_u: Add dummy serial clock and aliases entry for uart Palmer Dabbelt 2019-09-18 14:55 ` [Qemu-riscv] " Palmer Dabbelt 2019-09-18 14:55 ` [Qemu-devel] [PULL 03/48] riscv: sifive_u: Fix clock-names property for ethernet node Palmer Dabbelt 2019-09-18 14:55 ` [Qemu-riscv] " Palmer Dabbelt 2019-09-18 14:55 ` [Qemu-devel] [PULL 04/48] target/riscv/pmp: Restrict priviledged PMP to system-mode emulation Palmer Dabbelt 2019-09-18 14:55 ` [Qemu-riscv] " Palmer Dabbelt 2019-09-18 14:55 ` [Qemu-devel] [PULL 05/48] target/riscv/pmp: Convert qemu_log_mask(LOG_TRACE) to trace events Palmer Dabbelt 2019-09-18 14:55 ` [Qemu-riscv] " Palmer Dabbelt 2019-09-18 14:55 ` [Qemu-devel] [PULL 06/48] riscv: plic: Remove unused interrupt functions Palmer Dabbelt 2019-09-18 14:55 ` [Qemu-riscv] " Palmer Dabbelt 2019-09-18 14:55 ` [Qemu-devel] [PULL 07/48] target/riscv: Create function to test if FP is enabled Palmer Dabbelt 2019-09-18 14:55 ` [Qemu-riscv] " Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-devel] [PULL 08/48] target/riscv: Update the Hypervisor CSRs to v0.4 Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-devel] [PULL 09/48] riscv: rv32: Root page table address can be larger than 32-bit Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-devel] [PULL 10/48] riscv: Add a helper routine for finding firmware Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-devel] [PULL 11/48] riscv: Resolve full path of the given bios image Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt 2019-09-24 10:17 ` Peter Maydell 2019-09-24 10:17 ` Peter Maydell 2019-10-02 21:38 ` Alistair Francis 2019-10-02 21:38 ` Alistair Francis 2019-09-18 14:56 ` [Qemu-devel] [PULL 12/48] riscv: hmp: Add a command to show virtual memory mappings Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-devel] [PULL 13/48] riscv: sifive_test: Add reset functionality Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-devel] [PULL 14/48] riscv: hw: Remove duplicated "hw/hw.h" inclusion Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-devel] [PULL 15/48] riscv: hw: Remove superfluous "linux, phandle" property Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-devel] [PULL 16/48] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-devel] [PULL 17/48] riscv: hw: Remove not needed PLIC properties in device tree Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-devel] [PULL 18/48] riscv: hw: Change create_fdt() to return void Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-devel] [PULL 19/48] riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) instead Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-devel] [PULL 20/48] riscv: hw: Remove the unnecessary include of target/riscv/cpu.h Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-devel] [PULL 21/48] riscv: roms: Remove executable attribute of opensbi images Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-devel] [PULL 22/48] riscv: sifive_u: Remove the unnecessary include of prci header Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-devel] [PULL 23/48] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h} Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-devel] [PULL 24/48] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-devel] [PULL 25/48] riscv: sifive_e: prci: Update the PRCI register block size Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-devel] [PULL 26/48] riscv: sifive_e: Drop sifive_mmio_emulate() Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-devel] [PULL 27/48] riscv: Add a sifive_cpu.h to include both E and U cpu type defines Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-devel] [PULL 28/48] riscv: hart: Extract hart realize to a separate routine Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-devel] [PULL 29/48] riscv: hart: Add a "hartid-base" property to RISC-V hart array Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-devel] [PULL 30/48] riscv: sifive_u: Set the minimum number of cpus to 2 Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-devel] [PULL 31/48] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-devel] [PULL 32/48] riscv: sifive_u: Update PLIC hart topology configuration string Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-devel] [PULL 33/48] riscv: sifive: Implement PRCI model for FU540 Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-devel] [PULL 34/48] riscv: sifive_u: Generate hfclk and rtcclk nodes Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-devel] [PULL 35/48] riscv: sifive_u: Add PRCI block to the SoC Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-devel] [PULL 36/48] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-devel] [PULL 37/48] riscv: sifive_u: Update UART base addresses and IRQs Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-devel] [PULL 38/48] riscv: sifive_u: Change UART node name in device tree Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-devel] [PULL 39/48] riscv: roms: Update default bios for sifive_u machine Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt 2019-09-18 14:56 ` Palmer Dabbelt [this message] 2019-09-18 14:56 ` [Qemu-riscv] [PULL 40/48] riscv: sifive: Implement a model for SiFive FU540 OTP Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-devel] [PULL 41/48] riscv: sifive_u: Instantiate OTP memory with a serial number Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-devel] [PULL 42/48] riscv: sifive_u: Fix broken GEM support Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-devel] [PULL 43/48] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-devel] [PULL 44/48] riscv: sifive_u: Update model and compatible strings in device tree Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-devel] [PULL 45/48] target/riscv: Use both register name and ABI name Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-devel] [PULL 46/48] target/riscv: Fix mstatus dirty mask Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-devel] [PULL 47/48] target/riscv: Use TB_FLAGS_MSTATUS_FS for floating point Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-devel] [PULL 48/48] gdbstub: riscv: fix the fflags registers Palmer Dabbelt 2019-09-18 14:56 ` [Qemu-riscv] " Palmer Dabbelt 2019-09-19 12:26 ` [Qemu-devel] [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1, v3 Peter Maydell 2019-09-19 12:26 ` [Qemu-riscv] " Peter Maydell
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