[RFC PATCH 01/13] kvm: Enable MTRR to work with GFNs with perm bits

From: Rick Edgecombe <rick.p.edgecombe@intel.com>
To: kvm@vger.kernel.org, linux-kernel@vger.kernel.org,
	x86@kernel.org, linux-mm@kvack.org, luto@kernel.org,
	peterz@infradead.org, dave.hansen@intel.com, pbonzini@redhat.com,
	sean.j.christopherson@intel.com, keescook@chromium.org
Cc: kristen@linux.intel.com, deneen.t.dock@intel.com,
	Rick Edgecombe <rick.p.edgecombe@intel.com>
Subject: [RFC PATCH 01/13] kvm: Enable MTRR to work with GFNs with perm bits
Date: Thu,  3 Oct 2019 14:23:48 -0700	[thread overview]
Message-ID: <20191003212400.31130-2-rick.p.edgecombe@intel.com> (raw)
In-Reply-To: <20191003212400.31130-1-rick.p.edgecombe@intel.com>

Mask gfn by maxphyaddr in kvm_mtrr_get_guest_memory_type so that the
guests view of gfn is used when high bits of the physical memory are
used as extra permissions bits. This supports the KVM XO feature.

TODO: Since MTRR is emulated using EPT permissions, the XO version of
the gpa range will not inherrit the MTRR type with this implementation.
There shouldn't be any legacy use of KVM XO, but hypothetically it could
interfere with the uncacheable MTRR type.

Signed-off-by: Rick Edgecombe <rick.p.edgecombe@intel.com>
---
 arch/x86/kvm/mtrr.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/x86/kvm/mtrr.c b/arch/x86/kvm/mtrr.c
index 25ce3edd1872..da38f3b83e51 100644
--- a/arch/x86/kvm/mtrr.c
+++ b/arch/x86/kvm/mtrr.c
@@ -621,6 +621,14 @@ u8 kvm_mtrr_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn)
 	const int wt_wb_mask = (1 << MTRR_TYPE_WRBACK)
 			       | (1 << MTRR_TYPE_WRTHROUGH);
 
+	/*
+	 * Handle situations where gfn bits are used as permissions bits by
+	 * masking KVMs view of the gfn with the guests physical address bits
+	 * in order to match the guests view of physical address. For normal
+	 * situations this will have no effect.
+	 */
+	gfn &= (1ULL << (cpuid_maxphyaddr(vcpu) - PAGE_SHIFT));
+
 	start = gfn_to_gpa(gfn);
 	end = start + PAGE_SIZE;
 
-- 
2.17.1

