From: Rick Edgecombe <rick.p.edgecombe@intel.com>
To: kvm@vger.kernel.org, linux-kernel@vger.kernel.org,
x86@kernel.org, linux-mm@kvack.org, luto@kernel.org,
peterz@infradead.org, dave.hansen@intel.com, pbonzini@redhat.com,
sean.j.christopherson@intel.com, keescook@chromium.org
Cc: kristen@linux.intel.com, deneen.t.dock@intel.com,
Rick Edgecombe <rick.p.edgecombe@intel.com>
Subject: [RFC PATCH 02/13] kvm: Add support for X86_FEATURE_KVM_XO
Date: Thu, 3 Oct 2019 14:23:49 -0700 [thread overview]
Message-ID: <20191003212400.31130-3-rick.p.edgecombe@intel.com> (raw)
In-Reply-To: <20191003212400.31130-1-rick.p.edgecombe@intel.com>
Add X86_FEATURE_KVM_XO which reduces the physical address bits exposed by
CPUID and uses the hosts highest physical address bit as an XO/NR
permission bit in the guest page tables. Adjust reserved mask so KVM guest
page tables walks are aware this bit is not reserved.
Signed-off-by: Rick Edgecombe <rick.p.edgecombe@intel.com>
---
arch/x86/include/asm/cpufeature.h | 1 +
arch/x86/include/asm/cpufeatures.h | 3 +++
arch/x86/include/uapi/asm/kvm_para.h | 3 +++
arch/x86/kvm/cpuid.c | 7 +++++++
arch/x86/kvm/cpuid.h | 1 +
arch/x86/kvm/mmu.c | 18 ++++++++++++------
6 files changed, 27 insertions(+), 6 deletions(-)
diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 58acda503817..17127ffbc2a2 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -30,6 +30,7 @@ enum cpuid_leafs
CPUID_7_ECX,
CPUID_8000_0007_EBX,
CPUID_7_EDX,
+ CPUID_4000_0030_EAX
};
#ifdef CONFIG_X86_FEATURE_NAMES
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index e880f2408e29..7ba217e894ea 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -364,6 +364,9 @@
#define X86_FEATURE_ARCH_CAPABILITIES (18*32+29) /* IA32_ARCH_CAPABILITIES MSR (Intel) */
#define X86_FEATURE_SPEC_CTRL_SSBD (18*32+31) /* "" Speculative Store Bypass Disable */
+/* KVM-defined CPU features, CPUID level 0x40000030 (EAX), word 19 */
+#define X86_FEATURE_KVM_XO (19*32+0) /* KVM EPT based execute only memory support */
+
/*
* BUG word(s)
*/
diff --git a/arch/x86/include/uapi/asm/kvm_para.h b/arch/x86/include/uapi/asm/kvm_para.h
index 2a8e0b6b9805..ecff0ff25cf4 100644
--- a/arch/x86/include/uapi/asm/kvm_para.h
+++ b/arch/x86/include/uapi/asm/kvm_para.h
@@ -34,6 +34,9 @@
#define KVM_HINTS_REALTIME 0
+#define KVM_CPUID_FEAT_GENERIC 0x40000030
+#define KVM_FEATURE_GENERIC_XO 0
+
/* The last 8 bits are used to indicate how to interpret the flags field
* in pvclock structure. If no bits are set, all flags are ignored.
*/
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index 22c2720cd948..bcbf3f93602d 100644
--- a/arch/x86/kvm/cpuid.c
+++ b/arch/x86/kvm/cpuid.c
@@ -700,6 +700,12 @@ static inline int __do_cpuid_func(struct kvm_cpuid_entry2 *entry, u32 function,
if (sched_info_on())
entry->eax |= (1 << KVM_FEATURE_STEAL_TIME);
+ entry->ebx = 0;
+ entry->ecx = 0;
+ entry->edx = 0;
+ break;
+ case KVM_CPUID_FEAT_GENERIC:
+ entry->eax = (1 << KVM_FEATURE_GENERIC_XO);
entry->ebx = 0;
entry->ecx = 0;
entry->edx = 0;
@@ -845,6 +851,7 @@ int kvm_dev_ioctl_get_cpuid(struct kvm_cpuid2 *cpuid,
{ .func = 0x80000000 },
{ .func = 0xC0000000, .qualifier = is_centaur_cpu },
{ .func = KVM_CPUID_SIGNATURE },
+ { .func = KVM_CPUID_FEAT_GENERIC },
};
if (cpuid->nent < 1)
diff --git a/arch/x86/kvm/cpuid.h b/arch/x86/kvm/cpuid.h
index d78a61408243..c36d462a0e01 100644
--- a/arch/x86/kvm/cpuid.h
+++ b/arch/x86/kvm/cpuid.h
@@ -53,6 +53,7 @@ static const struct cpuid_reg reverse_cpuid[] = {
[CPUID_7_ECX] = { 7, 0, CPUID_ECX},
[CPUID_8000_0007_EBX] = {0x80000007, 0, CPUID_EBX},
[CPUID_7_EDX] = { 7, 0, CPUID_EDX},
+ [CPUID_4000_0030_EAX] = {0x40000030, 0, CPUID_EAX},
};
static __always_inline struct cpuid_reg x86_feature_cpuid(unsigned x86_feature)
diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c
index a63964e7cec7..e44a8053af78 100644
--- a/arch/x86/kvm/mmu.c
+++ b/arch/x86/kvm/mmu.c
@@ -4358,12 +4358,15 @@ static void
__reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
struct rsvd_bits_validate *rsvd_check,
int maxphyaddr, int level, bool nx, bool gbpages,
- bool pse, bool amd)
+ bool pse, bool amd, bool xo)
{
u64 exb_bit_rsvd = 0;
u64 gbpages_bit_rsvd = 0;
u64 nonleaf_bit8_rsvd = 0;
+ /* Adjust maxphyaddr to include the XO bit if in use */
+ maxphyaddr += xo;
+
rsvd_check->bad_mt_xwr = 0;
if (!nx)
@@ -4448,10 +4451,12 @@ static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
struct kvm_mmu *context)
{
__reset_rsvds_bits_mask(vcpu, &context->guest_rsvd_check,
- cpuid_maxphyaddr(vcpu), context->root_level,
+ cpuid_maxphyaddr(vcpu),
+ context->root_level,
context->nx,
guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES),
- is_pse(vcpu), guest_cpuid_is_amd(vcpu));
+ is_pse(vcpu), guest_cpuid_is_amd(vcpu),
+ guest_cpuid_has(vcpu, X86_FEATURE_KVM_XO));
}
static void
@@ -4520,7 +4525,7 @@ reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, struct kvm_mmu *context)
shadow_phys_bits,
context->shadow_root_level, uses_nx,
guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES),
- is_pse(vcpu), true);
+ is_pse(vcpu), true, false);
if (!shadow_me_mask)
return;
@@ -4557,7 +4562,7 @@ reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
shadow_phys_bits,
context->shadow_root_level, false,
boot_cpu_has(X86_FEATURE_GBPAGES),
- true, true);
+ true, true, false);
else
__reset_rsvds_bits_mask_ept(shadow_zero_check,
shadow_phys_bits,
@@ -4818,7 +4823,8 @@ static union kvm_mmu_extended_role kvm_calc_mmu_role_ext(struct kvm_vcpu *vcpu)
ext.cr4_pse = !!is_pse(vcpu);
ext.cr4_pke = !!kvm_read_cr4_bits(vcpu, X86_CR4_PKE);
ext.cr4_la57 = !!kvm_read_cr4_bits(vcpu, X86_CR4_LA57);
- ext.maxphyaddr = cpuid_maxphyaddr(vcpu);
+ ext.maxphyaddr = cpuid_maxphyaddr(vcpu)
+ + guest_cpuid_has(vcpu, X86_FEATURE_KVM_XO);
ext.valid = 1;
--
2.17.1
next prev parent reply other threads:[~2019-10-03 21:39 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-03 21:23 [RFC PATCH 00/13] XOM for KVM guest userspace Rick Edgecombe
2019-10-03 21:23 ` [RFC PATCH 01/13] kvm: Enable MTRR to work with GFNs with perm bits Rick Edgecombe
2019-10-14 6:47 ` Yu Zhang
2019-10-14 18:44 ` Edgecombe, Rick P
2019-10-03 21:23 ` Rick Edgecombe [this message]
2019-10-03 21:23 ` [RFC PATCH 03/13] kvm: Add XO memslot type Rick Edgecombe
2019-10-04 7:27 ` Paolo Bonzini
2019-10-04 19:06 ` Edgecombe, Rick P
2019-10-06 16:15 ` Paolo Bonzini
2019-10-03 21:23 ` [RFC PATCH 04/13] kvm, vmx: Add support for gva exit qualification Rick Edgecombe
2019-10-03 21:23 ` [RFC PATCH 05/13] kvm: Add #PF injection for KVM XO Rick Edgecombe
2019-10-04 7:42 ` Paolo Bonzini
2019-10-04 19:11 ` Edgecombe, Rick P
2019-10-03 21:23 ` [RFC PATCH 06/13] kvm: Add KVM_CAP_EXECONLY_MEM Rick Edgecombe
2019-10-04 7:24 ` Paolo Bonzini
2019-10-04 19:11 ` Edgecombe, Rick P
2019-10-03 21:23 ` [RFC PATCH 07/13] kvm: Add docs for KVM_CAP_EXECONLY_MEM Rick Edgecombe
2019-10-03 21:23 ` [RFC PATCH 08/13] x86/boot: Rename USE_EARLY_PGTABLE_L5 Rick Edgecombe
2019-10-03 21:23 ` [RFC PATCH 09/13] x86/cpufeature: Add detection of KVM XO Rick Edgecombe
2019-10-29 23:33 ` Kees Cook
2019-10-29 23:52 ` Edgecombe, Rick P
2019-10-30 14:55 ` Sean Christopherson
2019-10-30 21:02 ` Edgecombe, Rick P
2019-10-03 21:23 ` [RFC PATCH 10/13] x86/mm: Add NR page bit for " Rick Edgecombe
2019-10-04 7:33 ` Paolo Bonzini
2019-10-03 21:23 ` [RFC PATCH 11/13] x86, ptdump: Add NR bit to page table dump Rick Edgecombe
2019-10-03 21:23 ` [RFC PATCH 12/13] mmap: Add XO support for KVM XO Rick Edgecombe
2019-10-04 7:34 ` Paolo Bonzini
2019-10-04 19:12 ` Edgecombe, Rick P
2019-10-03 21:24 ` [RFC PATCH 13/13] x86/Kconfig: Add Kconfig for KVM based XO Rick Edgecombe
2019-10-29 23:36 ` Kees Cook
2019-10-30 0:01 ` Edgecombe, Rick P
2019-10-30 18:36 ` Kees Cook
2019-10-04 7:22 ` [RFC PATCH 00/13] XOM for KVM guest userspace Paolo Bonzini
2019-10-04 19:03 ` Edgecombe, Rick P
2019-10-04 14:56 ` Andy Lutomirski
2019-10-04 14:56 ` Andy Lutomirski
2019-10-04 20:09 ` Edgecombe, Rick P
2019-10-05 1:33 ` Andy Lutomirski
2019-10-05 1:33 ` Andy Lutomirski
2019-10-07 18:14 ` Edgecombe, Rick P
2019-10-29 23:40 ` Kees Cook
2019-10-30 0:27 ` Edgecombe, Rick P
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20191003212400.31130-3-rick.p.edgecombe@intel.com \
--to=rick.p.edgecombe@intel.com \
--cc=dave.hansen@intel.com \
--cc=deneen.t.dock@intel.com \
--cc=keescook@chromium.org \
--cc=kristen@linux.intel.com \
--cc=kvm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mm@kvack.org \
--cc=luto@kernel.org \
--cc=pbonzini@redhat.com \
--cc=peterz@infradead.org \
--cc=sean.j.christopherson@intel.com \
--cc=x86@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.