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From: Thierry Reding <thierry.reding@gmail.com>
To: Manasi Navare <manasi.d.navare@intel.com>
Cc: intel-gfx@lists.freedesktop.org,
	Harry Wentland <harry.wentland@amd.com>,
	dri-devel@lists.freedesktop.org
Subject: Re: [PATCH] drm/dp: Add function to parse EDID descriptors for adaptive sync limits
Date: Thu, 24 Oct 2019 12:31:06 +0200	[thread overview]
Message-ID: <20191024103106.GA2825247@ulmo> (raw)
In-Reply-To: <20191024000041.7391-1-manasi.d.navare@intel.com>


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On Wed, Oct 23, 2019 at 05:00:41PM -0700, Manasi Navare wrote:
> Adaptive Sync is a VESA feature so add a DRM core helper to parse
> the EDID's detailed descritors to obtain the adaptive sync monitor range.
> Store this info as part fo drm_display_info so it can be used
> across all drivers.
> This part of the code is stripped out of amdgpu's function
> amdgpu_dm_update_freesync_caps() to make it generic and be used
> across all DRM drivers
> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Harry Wentland <harry.wentland@amd.com>
> Cc: Clinton A Taylor <clinton.a.taylor@intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> ---
>  drivers/gpu/drm/drm_edid.c  | 49 +++++++++++++++++++++++++++++++++++++
>  include/drm/drm_connector.h | 25 +++++++++++++++++++
>  include/drm/drm_edid.h      |  2 ++
>  3 files changed, 76 insertions(+)
> 
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> index 474ac04d5600..97dd1200773e 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -4707,6 +4707,52 @@ static void drm_parse_cea_ext(struct drm_connector *connector,
>  	}
>  }
>  
> +void drm_get_adaptive_sync_limits(struct drm_connector *connector,
> +				  const struct edid *edid)
> +{
> +	struct drm_display_info *info = &connector->display_info;
> +	const struct detailed_timing *timing;
> +	const struct detailed_non_pixel *data;
> +	const struct detailed_data_monitor_range *range;
> +	int i;

This can be unsigned int.

> +
> +	/*
> +	 * Restrict Adaptive Sync only for dp and edp
> +	 */
> +	if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort &&
> +	    connector->connector_type != DRM_MODE_CONNECTOR_eDP)
> +		return;
> +
> +	if (edid->version <= 1 && !(edid->version == 1 && edid->revision > 1))
> +		return;
> +
> +	for (i = 0; i < 4; i++) {
> +		timing  = &edid->detailed_timings[i];
> +		data    = &timing->data.other_data;
> +		range   = &data->data.range;
> +		/*
> +		 * Check if monitor has continuous frequency mode
> +		 */
> +		if (data->type != EDID_DETAIL_MONITOR_RANGE)
> +			continue;
> +		/*
> +		 * Check for flag range limits only. If flag == 1 then
> +		 * no additional timing information provided.
> +		 * Default GTF, GTF Secondary curve and CVT are not
> +		 * supported
> +		 */
> +		if (range->flags != 1)
> +			continue;
> +
> +		info->adaptive_sync.min_vfreq = range->min_vfreq;
> +		info->adaptive_sync.max_vfreq = range->max_vfreq;
> +		info->adaptive_sync.pixel_clock_mhz =
> +			range->pixel_clock_mhz * 10;
> +		break;
> +	}
> +}
> +EXPORT_SYMBOL(drm_get_adaptive_sync_limits);
> +
>  /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
>   * all of the values which would have been set from EDID
>   */
> @@ -4728,6 +4774,7 @@ drm_reset_display_info(struct drm_connector *connector)
>  	memset(&info->hdmi, 0, sizeof(info->hdmi));
>  
>  	info->non_desktop = 0;
> +	memset(&info->adaptive_sync, 0, sizeof(info->adaptive_sync));
>  }
>  
>  u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid)
> @@ -4743,6 +4790,8 @@ u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edi
>  
>  	info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP);
>  
> +	drm_get_adaptive_sync_limits(connector, edid);
> +
>  	DRM_DEBUG_KMS("non_desktop set to %d\n", info->non_desktop);
>  
>  	if (edid->revision < 3)
> diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
> index 5f8c3389d46f..a27a84270d8d 100644
> --- a/include/drm/drm_connector.h
> +++ b/include/drm/drm_connector.h
> @@ -254,6 +254,26 @@ enum drm_panel_orientation {
>  	DRM_MODE_PANEL_ORIENTATION_RIGHT_UP,
>  };
>  
> +/**
> + * struct drm_adaptive_sync_info - Panel's Adaptive Sync capabilities for
> + * &drm_display_info
> + *
> + * This struct is used to store a Panel's Adaptive Sync capabilities
> + * as parsed from EDID's detailed monitor range descriptor block.
> + *
> + * @min_vfreq: This is the min supported refresh rate in Hz from
> + *             EDID's detailed monitor range.
> + * @max_vfreq: This is the max supported refresh rate in Hz from
> + *             EDID's detailed monitor range
> + * @pixel_clock_mhz: This is the dotclock in MHz from
> + *                   EDID's detailed monitor range
> + */
> +struct drm_adaptive_sync_info {
> +	int min_vfreq;
> +	int max_vfreq;
> +	int pixel_clock_mhz;

Any reason why these can't be unsigned? Also, does it perhaps make sense
to store the pixel clock as kHz like we do everywhere else?

Thierry

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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

WARNING: multiple messages have this Message-ID (diff)
From: Thierry Reding <thierry.reding@gmail.com>
To: Manasi Navare <manasi.d.navare@intel.com>
Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH] drm/dp: Add function to parse EDID descriptors for adaptive sync limits
Date: Thu, 24 Oct 2019 12:31:06 +0200	[thread overview]
Message-ID: <20191024103106.GA2825247@ulmo> (raw)
Message-ID: <20191024103106.JVpezCtPbe5oqqKGYE5UC5umAT29RuEg7JH1UDNMf8o@z> (raw)
In-Reply-To: <20191024000041.7391-1-manasi.d.navare@intel.com>


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On Wed, Oct 23, 2019 at 05:00:41PM -0700, Manasi Navare wrote:
> Adaptive Sync is a VESA feature so add a DRM core helper to parse
> the EDID's detailed descritors to obtain the adaptive sync monitor range.
> Store this info as part fo drm_display_info so it can be used
> across all drivers.
> This part of the code is stripped out of amdgpu's function
> amdgpu_dm_update_freesync_caps() to make it generic and be used
> across all DRM drivers
> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Harry Wentland <harry.wentland@amd.com>
> Cc: Clinton A Taylor <clinton.a.taylor@intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> ---
>  drivers/gpu/drm/drm_edid.c  | 49 +++++++++++++++++++++++++++++++++++++
>  include/drm/drm_connector.h | 25 +++++++++++++++++++
>  include/drm/drm_edid.h      |  2 ++
>  3 files changed, 76 insertions(+)
> 
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> index 474ac04d5600..97dd1200773e 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -4707,6 +4707,52 @@ static void drm_parse_cea_ext(struct drm_connector *connector,
>  	}
>  }
>  
> +void drm_get_adaptive_sync_limits(struct drm_connector *connector,
> +				  const struct edid *edid)
> +{
> +	struct drm_display_info *info = &connector->display_info;
> +	const struct detailed_timing *timing;
> +	const struct detailed_non_pixel *data;
> +	const struct detailed_data_monitor_range *range;
> +	int i;

This can be unsigned int.

> +
> +	/*
> +	 * Restrict Adaptive Sync only for dp and edp
> +	 */
> +	if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort &&
> +	    connector->connector_type != DRM_MODE_CONNECTOR_eDP)
> +		return;
> +
> +	if (edid->version <= 1 && !(edid->version == 1 && edid->revision > 1))
> +		return;
> +
> +	for (i = 0; i < 4; i++) {
> +		timing  = &edid->detailed_timings[i];
> +		data    = &timing->data.other_data;
> +		range   = &data->data.range;
> +		/*
> +		 * Check if monitor has continuous frequency mode
> +		 */
> +		if (data->type != EDID_DETAIL_MONITOR_RANGE)
> +			continue;
> +		/*
> +		 * Check for flag range limits only. If flag == 1 then
> +		 * no additional timing information provided.
> +		 * Default GTF, GTF Secondary curve and CVT are not
> +		 * supported
> +		 */
> +		if (range->flags != 1)
> +			continue;
> +
> +		info->adaptive_sync.min_vfreq = range->min_vfreq;
> +		info->adaptive_sync.max_vfreq = range->max_vfreq;
> +		info->adaptive_sync.pixel_clock_mhz =
> +			range->pixel_clock_mhz * 10;
> +		break;
> +	}
> +}
> +EXPORT_SYMBOL(drm_get_adaptive_sync_limits);
> +
>  /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
>   * all of the values which would have been set from EDID
>   */
> @@ -4728,6 +4774,7 @@ drm_reset_display_info(struct drm_connector *connector)
>  	memset(&info->hdmi, 0, sizeof(info->hdmi));
>  
>  	info->non_desktop = 0;
> +	memset(&info->adaptive_sync, 0, sizeof(info->adaptive_sync));
>  }
>  
>  u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid)
> @@ -4743,6 +4790,8 @@ u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edi
>  
>  	info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP);
>  
> +	drm_get_adaptive_sync_limits(connector, edid);
> +
>  	DRM_DEBUG_KMS("non_desktop set to %d\n", info->non_desktop);
>  
>  	if (edid->revision < 3)
> diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
> index 5f8c3389d46f..a27a84270d8d 100644
> --- a/include/drm/drm_connector.h
> +++ b/include/drm/drm_connector.h
> @@ -254,6 +254,26 @@ enum drm_panel_orientation {
>  	DRM_MODE_PANEL_ORIENTATION_RIGHT_UP,
>  };
>  
> +/**
> + * struct drm_adaptive_sync_info - Panel's Adaptive Sync capabilities for
> + * &drm_display_info
> + *
> + * This struct is used to store a Panel's Adaptive Sync capabilities
> + * as parsed from EDID's detailed monitor range descriptor block.
> + *
> + * @min_vfreq: This is the min supported refresh rate in Hz from
> + *             EDID's detailed monitor range.
> + * @max_vfreq: This is the max supported refresh rate in Hz from
> + *             EDID's detailed monitor range
> + * @pixel_clock_mhz: This is the dotclock in MHz from
> + *                   EDID's detailed monitor range
> + */
> +struct drm_adaptive_sync_info {
> +	int min_vfreq;
> +	int max_vfreq;
> +	int pixel_clock_mhz;

Any reason why these can't be unsigned? Also, does it perhaps make sense
to store the pixel clock as kHz like we do everywhere else?

Thierry

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_______________________________________________
dri-devel mailing list
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WARNING: multiple messages have this Message-ID (diff)
From: Thierry Reding <thierry.reding@gmail.com>
To: Manasi Navare <manasi.d.navare@intel.com>
Cc: intel-gfx@lists.freedesktop.org,
	Harry Wentland <harry.wentland@amd.com>,
	dri-devel@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH] drm/dp: Add function to parse EDID descriptors for adaptive sync limits
Date: Thu, 24 Oct 2019 12:31:06 +0200	[thread overview]
Message-ID: <20191024103106.GA2825247@ulmo> (raw)
Message-ID: <20191024103106.HOSdycnVxvsAd5WRmUTau8rbYSHifK71FBBVgROnwMM@z> (raw)
In-Reply-To: <20191024000041.7391-1-manasi.d.navare@intel.com>


[-- Attachment #1.1: Type: text/plain, Size: 4695 bytes --]

On Wed, Oct 23, 2019 at 05:00:41PM -0700, Manasi Navare wrote:
> Adaptive Sync is a VESA feature so add a DRM core helper to parse
> the EDID's detailed descritors to obtain the adaptive sync monitor range.
> Store this info as part fo drm_display_info so it can be used
> across all drivers.
> This part of the code is stripped out of amdgpu's function
> amdgpu_dm_update_freesync_caps() to make it generic and be used
> across all DRM drivers
> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Harry Wentland <harry.wentland@amd.com>
> Cc: Clinton A Taylor <clinton.a.taylor@intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> ---
>  drivers/gpu/drm/drm_edid.c  | 49 +++++++++++++++++++++++++++++++++++++
>  include/drm/drm_connector.h | 25 +++++++++++++++++++
>  include/drm/drm_edid.h      |  2 ++
>  3 files changed, 76 insertions(+)
> 
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> index 474ac04d5600..97dd1200773e 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -4707,6 +4707,52 @@ static void drm_parse_cea_ext(struct drm_connector *connector,
>  	}
>  }
>  
> +void drm_get_adaptive_sync_limits(struct drm_connector *connector,
> +				  const struct edid *edid)
> +{
> +	struct drm_display_info *info = &connector->display_info;
> +	const struct detailed_timing *timing;
> +	const struct detailed_non_pixel *data;
> +	const struct detailed_data_monitor_range *range;
> +	int i;

This can be unsigned int.

> +
> +	/*
> +	 * Restrict Adaptive Sync only for dp and edp
> +	 */
> +	if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort &&
> +	    connector->connector_type != DRM_MODE_CONNECTOR_eDP)
> +		return;
> +
> +	if (edid->version <= 1 && !(edid->version == 1 && edid->revision > 1))
> +		return;
> +
> +	for (i = 0; i < 4; i++) {
> +		timing  = &edid->detailed_timings[i];
> +		data    = &timing->data.other_data;
> +		range   = &data->data.range;
> +		/*
> +		 * Check if monitor has continuous frequency mode
> +		 */
> +		if (data->type != EDID_DETAIL_MONITOR_RANGE)
> +			continue;
> +		/*
> +		 * Check for flag range limits only. If flag == 1 then
> +		 * no additional timing information provided.
> +		 * Default GTF, GTF Secondary curve and CVT are not
> +		 * supported
> +		 */
> +		if (range->flags != 1)
> +			continue;
> +
> +		info->adaptive_sync.min_vfreq = range->min_vfreq;
> +		info->adaptive_sync.max_vfreq = range->max_vfreq;
> +		info->adaptive_sync.pixel_clock_mhz =
> +			range->pixel_clock_mhz * 10;
> +		break;
> +	}
> +}
> +EXPORT_SYMBOL(drm_get_adaptive_sync_limits);
> +
>  /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
>   * all of the values which would have been set from EDID
>   */
> @@ -4728,6 +4774,7 @@ drm_reset_display_info(struct drm_connector *connector)
>  	memset(&info->hdmi, 0, sizeof(info->hdmi));
>  
>  	info->non_desktop = 0;
> +	memset(&info->adaptive_sync, 0, sizeof(info->adaptive_sync));
>  }
>  
>  u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid)
> @@ -4743,6 +4790,8 @@ u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edi
>  
>  	info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP);
>  
> +	drm_get_adaptive_sync_limits(connector, edid);
> +
>  	DRM_DEBUG_KMS("non_desktop set to %d\n", info->non_desktop);
>  
>  	if (edid->revision < 3)
> diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
> index 5f8c3389d46f..a27a84270d8d 100644
> --- a/include/drm/drm_connector.h
> +++ b/include/drm/drm_connector.h
> @@ -254,6 +254,26 @@ enum drm_panel_orientation {
>  	DRM_MODE_PANEL_ORIENTATION_RIGHT_UP,
>  };
>  
> +/**
> + * struct drm_adaptive_sync_info - Panel's Adaptive Sync capabilities for
> + * &drm_display_info
> + *
> + * This struct is used to store a Panel's Adaptive Sync capabilities
> + * as parsed from EDID's detailed monitor range descriptor block.
> + *
> + * @min_vfreq: This is the min supported refresh rate in Hz from
> + *             EDID's detailed monitor range.
> + * @max_vfreq: This is the max supported refresh rate in Hz from
> + *             EDID's detailed monitor range
> + * @pixel_clock_mhz: This is the dotclock in MHz from
> + *                   EDID's detailed monitor range
> + */
> +struct drm_adaptive_sync_info {
> +	int min_vfreq;
> +	int max_vfreq;
> +	int pixel_clock_mhz;

Any reason why these can't be unsigned? Also, does it perhaps make sense
to store the pixel clock as kHz like we do everywhere else?

Thierry

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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  parent reply	other threads:[~2019-10-24 10:31 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-10-24  0:00 [PATCH] drm/dp: Add function to parse EDID descriptors for adaptive sync limits Manasi Navare
2019-10-24  0:00 ` [Intel-gfx] " Manasi Navare
2019-10-24  3:59 ` ✗ Fi.CI.BAT: failure for " Patchwork
2019-10-24  3:59   ` [Intel-gfx] " Patchwork
2019-10-24 10:31 ` Thierry Reding [this message]
2019-10-24 10:31   ` [Intel-gfx] [PATCH] " Thierry Reding
2019-10-24 10:31   ` Thierry Reding
2019-10-24 11:34   ` Ville Syrjälä
2019-10-24 11:34     ` [Intel-gfx] " Ville Syrjälä
2019-10-24 11:34     ` Ville Syrjälä
2019-10-24 13:54     ` Thierry Reding
2019-10-24 13:54       ` [Intel-gfx] " Thierry Reding
2019-10-24 13:54       ` Thierry Reding
2019-10-24 14:20       ` Ville Syrjälä
2019-10-24 14:20         ` [Intel-gfx] " Ville Syrjälä
2019-10-24 14:20         ` Ville Syrjälä
2019-10-24 14:40         ` Thierry Reding
2019-10-24 14:40           ` [Intel-gfx] " Thierry Reding
2019-10-24 14:40           ` Thierry Reding
2019-10-24 17:31         ` Manasi Navare
2019-10-24 17:31           ` Manasi Navare
2019-10-24 17:17   ` Manasi Navare
2019-10-24 17:17     ` Manasi Navare
2019-10-24 15:06 ` Harry Wentland
2019-10-24 15:06   ` [Intel-gfx] " Harry Wentland
2019-10-25 20:02   ` Manasi Navare
2019-10-25 20:02     ` [Intel-gfx] " Manasi Navare
2019-10-25 20:02     ` Manasi Navare

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