From: Christoph Hellwig <hch@lst.de> To: Palmer Dabbelt <palmer@sifive.com>, Paul Walmsley <paul.walmsley@sifive.com> Cc: Damien Le Moal <damien.lemoal@wdc.com>, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel <anup@brainfault.org> Subject: [PATCH 03/12] riscv: poison SBI calls for M-mode Date: Mon, 28 Oct 2019 13:10:34 +0100 [thread overview] Message-ID: <20191028121043.22934-4-hch@lst.de> (raw) In-Reply-To: <20191028121043.22934-1-hch@lst.de> There is no SBI when we run in M-mode, so fail the compile for any code trying to use SBI calls. Signed-off-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Anup Patel <anup@brainfault.org> --- arch/riscv/include/asm/sbi.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 21134b3ef404..b167af3e7470 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -8,6 +8,7 @@ #include <linux/types.h> +#ifdef CONFIG_RISCV_SBI #define SBI_SET_TIMER 0 #define SBI_CONSOLE_PUTCHAR 1 #define SBI_CONSOLE_GETCHAR 2 @@ -93,5 +94,5 @@ static inline void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask, { SBI_CALL_4(SBI_REMOTE_SFENCE_VMA_ASID, hart_mask, start, size, asid); } - -#endif +#endif /* CONFIG_RISCV_SBI */ +#endif /* _ASM_RISCV_SBI_H */ -- 2.20.1
WARNING: multiple messages have this Message-ID (diff)
From: Christoph Hellwig <hch@lst.de> To: Palmer Dabbelt <palmer@sifive.com>, Paul Walmsley <paul.walmsley@sifive.com> Cc: Anup Patel <anup@brainfault.org>, Damien Le Moal <damien.lemoal@wdc.com>, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 03/12] riscv: poison SBI calls for M-mode Date: Mon, 28 Oct 2019 13:10:34 +0100 [thread overview] Message-ID: <20191028121043.22934-4-hch@lst.de> (raw) In-Reply-To: <20191028121043.22934-1-hch@lst.de> There is no SBI when we run in M-mode, so fail the compile for any code trying to use SBI calls. Signed-off-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Anup Patel <anup@brainfault.org> --- arch/riscv/include/asm/sbi.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 21134b3ef404..b167af3e7470 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -8,6 +8,7 @@ #include <linux/types.h> +#ifdef CONFIG_RISCV_SBI #define SBI_SET_TIMER 0 #define SBI_CONSOLE_PUTCHAR 1 #define SBI_CONSOLE_GETCHAR 2 @@ -93,5 +94,5 @@ static inline void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask, { SBI_CALL_4(SBI_REMOTE_SFENCE_VMA_ASID, hart_mask, start, size, asid); } - -#endif +#endif /* CONFIG_RISCV_SBI */ +#endif /* _ASM_RISCV_SBI_H */ -- 2.20.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2019-10-28 12:10 UTC|newest] Thread overview: 80+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-10-28 12:10 RISC-V nommu support v6 Christoph Hellwig 2019-10-28 12:10 ` Christoph Hellwig 2019-10-28 12:10 ` [PATCH 01/12] riscv: abstract out CSR names for supervisor vs machine mode Christoph Hellwig 2019-10-28 12:10 ` Christoph Hellwig 2019-11-05 17:56 ` Paul Walmsley 2019-11-05 17:56 ` Paul Walmsley 2019-11-05 17:57 ` Paul Walmsley 2019-11-05 17:57 ` Paul Walmsley 2019-11-05 18:02 ` Marc Zyngier 2019-11-05 18:02 ` Marc Zyngier 2019-11-12 10:38 ` Thomas Gleixner 2019-11-12 10:38 ` Thomas Gleixner 2019-11-14 7:30 ` Paul Walmsley 2019-11-14 7:30 ` Paul Walmsley 2019-10-28 12:10 ` [PATCH 02/12] riscv: don't allow selecting SBI based drivers for M-mode Christoph Hellwig 2019-10-28 12:10 ` Christoph Hellwig 2019-11-14 7:31 ` Paul Walmsley 2019-11-14 7:31 ` Paul Walmsley 2019-10-28 12:10 ` Christoph Hellwig [this message] 2019-10-28 12:10 ` [PATCH 03/12] riscv: poison SBI calls " Christoph Hellwig 2019-10-31 23:55 ` Paul Walmsley 2019-10-31 23:55 ` Paul Walmsley 2019-10-28 12:10 ` [PATCH 04/12] riscv: cleanup the default power off implementation Christoph Hellwig 2019-10-28 12:10 ` Christoph Hellwig 2019-10-31 20:49 ` Paul Walmsley 2019-10-31 20:49 ` Paul Walmsley 2019-10-31 23:56 ` Paul Walmsley 2019-10-31 23:56 ` Paul Walmsley 2019-10-28 12:10 ` [PATCH 05/12] riscv: implement remote sfence.i using IPIs Christoph Hellwig 2019-10-28 12:10 ` Christoph Hellwig 2019-10-31 23:57 ` Paul Walmsley 2019-10-31 23:57 ` Paul Walmsley 2019-10-28 12:10 ` [PATCH 06/12] riscv: add support for MMIO access to the timer registers Christoph Hellwig 2019-10-28 12:10 ` Christoph Hellwig 2019-11-05 18:01 ` Paul Walmsley 2019-11-05 18:01 ` Paul Walmsley 2019-11-12 10:39 ` Thomas Gleixner 2019-11-12 10:39 ` Thomas Gleixner 2019-11-17 23:06 ` Paul Walmsley 2019-11-17 23:06 ` Paul Walmsley 2019-10-28 12:10 ` [PATCH 07/12] riscv: provide native clint access for M-mode Christoph Hellwig 2019-10-28 12:10 ` Christoph Hellwig 2019-10-28 12:10 ` [PATCH 08/12] riscv: read the hart ID from mhartid on boot Christoph Hellwig 2019-10-28 12:10 ` Christoph Hellwig 2019-10-28 12:10 ` [PATCH 09/12] riscv: clear the instruction cache and all registers when booting Christoph Hellwig 2019-10-28 12:10 ` Christoph Hellwig 2019-11-14 7:45 ` Paul Walmsley 2019-11-14 7:45 ` Paul Walmsley 2019-10-28 12:10 ` [PATCH 10/12] riscv: add nommu support Christoph Hellwig 2019-10-28 12:10 ` Christoph Hellwig 2019-11-17 23:13 ` Paul Walmsley 2019-11-17 23:13 ` Paul Walmsley 2019-12-16 22:03 ` David Abdurachmanov 2019-12-16 22:03 ` David Abdurachmanov 2019-12-17 3:18 ` Paul Walmsley 2019-12-17 3:18 ` Paul Walmsley 2019-10-28 12:10 ` [PATCH 11/12] riscv: provide a flat image loader Christoph Hellwig 2019-10-28 12:10 ` Christoph Hellwig 2019-11-17 23:14 ` Paul Walmsley 2019-11-17 23:14 ` Paul Walmsley 2019-10-28 12:10 ` [PATCH 12/12] riscv: disable the EFI PECOFF header for M-mode Christoph Hellwig 2019-10-28 12:10 ` Christoph Hellwig 2019-10-30 20:21 ` RISC-V nommu support v6 Paul Walmsley 2019-10-30 20:21 ` Paul Walmsley 2019-10-31 15:52 ` Christoph Hellwig 2019-10-31 15:52 ` Christoph Hellwig 2019-10-31 20:13 ` Paul Walmsley 2019-10-31 20:13 ` Paul Walmsley 2019-11-23 2:19 ` Paul Walmsley 2019-11-23 2:19 ` Paul Walmsley 2019-12-11 8:42 ` Greentime Hu 2019-12-11 8:42 ` Greentime Hu 2020-02-12 12:19 ` Greentime Hu 2020-02-12 12:19 ` Greentime Hu 2019-11-11 9:47 ` Christoph Hellwig 2019-11-11 9:47 ` Christoph Hellwig 2019-11-11 17:02 ` Paul Walmsley 2019-11-11 17:02 ` Paul Walmsley 2019-11-13 13:18 ` Christoph Hellwig 2019-11-13 13:18 ` Christoph Hellwig
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