From: "Uwe Kleine-König" <u.kleine-koenig@pengutronix.de> To: "Clément Péron" <peron.clem@gmail.com> Cc: Thierry Reding <thierry.reding@gmail.com>, Rob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>, Maxime Ripard <mripard@kernel.org>, Chen-Yu Tsai <wens@csie.org>, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jernej Skrabec <jernej.skrabec@siol.net> Subject: Re: [PATCH v2 4/7] pwm: sun4i: Add support to output source clock directly Date: Mon, 4 Nov 2019 09:38:35 +0100 [thread overview] Message-ID: <20191104083835.m2pd4fvhn2ze6bjt@pengutronix.de> (raw) In-Reply-To: <20191103203334.10539-5-peron.clem@gmail.com> On Sun, Nov 03, 2019 at 09:33:31PM +0100, Clément Péron wrote: > From: Jernej Skrabec <jernej.skrabec@siol.net> > > PWM core has an option to bypass whole logic and output unchanged source > clock as PWM output. This is achieved by enabling bypass bit. > > Note that when bypass is enabled, no other setting has any meaning, not > even enable bit. > > This mode of operation is needed to achieve high enough frequency to > serve as clock source for AC200 chip, which is integrated into same > package as H6 SoC. I think the , should be dropped. > Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> > Signed-off-by: Clément Péron <peron.clem@gmail.com> > --- > drivers/pwm/pwm-sun4i.c | 39 ++++++++++++++++++++++++++++++++++++++- > 1 file changed, 38 insertions(+), 1 deletion(-) > > diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c > index b5e7ac364f59..2441574674d9 100644 > --- a/drivers/pwm/pwm-sun4i.c > +++ b/drivers/pwm/pwm-sun4i.c > @@ -3,6 +3,10 @@ > * Driver for Allwinner sun4i Pulse Width Modulation Controller > * > * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com> > + * > + * Limitations: > + * - When outputing the source clock directly, the PWM logic will be bypassed > + * and the currently running period is not guaranted to be completed Typo: guaranted -> guaranteed > */ > > #include <linux/bitops.h> > @@ -73,6 +77,7 @@ static const u32 prescaler_table[] = { > > struct sun4i_pwm_data { > bool has_prescaler_bypass; > + bool has_direct_mod_clk_output; > unsigned int npwm; > }; > > @@ -118,6 +123,20 @@ static void sun4i_pwm_get_state(struct pwm_chip *chip, > > val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG); > > + /* > + * PWM chapter in H6 manual has a diagram which explains that if bypass > + * bit is set, no other setting has any meaning. Even more, experiment > + * proved that also enable bit is ignored in this case. > + */ > + if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) && > + data->has_direct_mod_clk_output) { > + state->period = DIV_ROUND_CLOSEST_ULL(NSEC_PER_SEC, clk_rate); > + state->duty_cycle = state->period / 2; > + state->polarity = PWM_POLARITY_NORMAL; > + state->enabled = true; > + return; > + } Not sure how the rest of sun4i_pwm_get_state behaves, but I would prefer to let .get_state() round up which together with .apply_state() rounding down yields sound behaviour. > + > if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) && > sun4i_pwm->data->has_prescaler_bypass) > prescaler = 1; > @@ -203,7 +222,8 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, > { > struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip); > struct pwm_state cstate; > - u32 ctrl; > + u32 ctrl, clk_rate; > + bool bypass; > int ret; > unsigned int delay_us; > unsigned long now; > @@ -218,6 +238,16 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, > } > } > > + /* > + * Although it would make much more sense to check for bypass in > + * sun4i_pwm_calculate(), value of bypass bit also depends on "enabled". > + * Period is allowed to be rounded up or down. > + */ > + clk_rate = clk_get_rate(sun4i_pwm->clk); > + bypass = ((state->period * clk_rate >= NSEC_PER_SEC && > + state->period * clk_rate < NSEC_PER_SEC + clk_rate) && > + state->enabled); I guess the compiler is smart enough here, but checking for state->enabled is cheaper than the other checks, so putting this at the start of the expression seems sensible. The comment doesn't match the code. You don't round up state->period. (This is good, please fix the comment.) I think dropping the check state->period * clk_rate < NSEC_PER_SEC + clk_rate would be fine, too. I'd like to have a check for state->duty_cycle * clk_rate >= NSEC_PER_SEC / 2 && state->duty_cycle * clk_rate < NSEC_PER_SEC here. If this isn't true rather disable the PWM or output a 100% duty cycle with a larger period. > + > spin_lock(&sun4i_pwm->ctrl_lock); > ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG); > Best regards Uwe -- Pengutronix e.K. | Uwe Kleine-König | Industrial Linux Solutions | http://www.pengutronix.de/ |
WARNING: multiple messages have this Message-ID (diff)
From: "Uwe Kleine-König" <u.kleine-koenig@pengutronix.de> To: "Clément Péron" <peron.clem@gmail.com> Cc: Mark Rutland <mark.rutland@arm.com>, linux-pwm@vger.kernel.org, Jernej Skrabec <jernej.skrabec@siol.net>, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Maxime Ripard <mripard@kernel.org>, Rob Herring <robh+dt@kernel.org>, Chen-Yu Tsai <wens@csie.org>, Thierry Reding <thierry.reding@gmail.com>, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v2 4/7] pwm: sun4i: Add support to output source clock directly Date: Mon, 4 Nov 2019 09:38:35 +0100 [thread overview] Message-ID: <20191104083835.m2pd4fvhn2ze6bjt@pengutronix.de> (raw) In-Reply-To: <20191103203334.10539-5-peron.clem@gmail.com> On Sun, Nov 03, 2019 at 09:33:31PM +0100, Clément Péron wrote: > From: Jernej Skrabec <jernej.skrabec@siol.net> > > PWM core has an option to bypass whole logic and output unchanged source > clock as PWM output. This is achieved by enabling bypass bit. > > Note that when bypass is enabled, no other setting has any meaning, not > even enable bit. > > This mode of operation is needed to achieve high enough frequency to > serve as clock source for AC200 chip, which is integrated into same > package as H6 SoC. I think the , should be dropped. > Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> > Signed-off-by: Clément Péron <peron.clem@gmail.com> > --- > drivers/pwm/pwm-sun4i.c | 39 ++++++++++++++++++++++++++++++++++++++- > 1 file changed, 38 insertions(+), 1 deletion(-) > > diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c > index b5e7ac364f59..2441574674d9 100644 > --- a/drivers/pwm/pwm-sun4i.c > +++ b/drivers/pwm/pwm-sun4i.c > @@ -3,6 +3,10 @@ > * Driver for Allwinner sun4i Pulse Width Modulation Controller > * > * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com> > + * > + * Limitations: > + * - When outputing the source clock directly, the PWM logic will be bypassed > + * and the currently running period is not guaranted to be completed Typo: guaranted -> guaranteed > */ > > #include <linux/bitops.h> > @@ -73,6 +77,7 @@ static const u32 prescaler_table[] = { > > struct sun4i_pwm_data { > bool has_prescaler_bypass; > + bool has_direct_mod_clk_output; > unsigned int npwm; > }; > > @@ -118,6 +123,20 @@ static void sun4i_pwm_get_state(struct pwm_chip *chip, > > val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG); > > + /* > + * PWM chapter in H6 manual has a diagram which explains that if bypass > + * bit is set, no other setting has any meaning. Even more, experiment > + * proved that also enable bit is ignored in this case. > + */ > + if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) && > + data->has_direct_mod_clk_output) { > + state->period = DIV_ROUND_CLOSEST_ULL(NSEC_PER_SEC, clk_rate); > + state->duty_cycle = state->period / 2; > + state->polarity = PWM_POLARITY_NORMAL; > + state->enabled = true; > + return; > + } Not sure how the rest of sun4i_pwm_get_state behaves, but I would prefer to let .get_state() round up which together with .apply_state() rounding down yields sound behaviour. > + > if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) && > sun4i_pwm->data->has_prescaler_bypass) > prescaler = 1; > @@ -203,7 +222,8 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, > { > struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip); > struct pwm_state cstate; > - u32 ctrl; > + u32 ctrl, clk_rate; > + bool bypass; > int ret; > unsigned int delay_us; > unsigned long now; > @@ -218,6 +238,16 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, > } > } > > + /* > + * Although it would make much more sense to check for bypass in > + * sun4i_pwm_calculate(), value of bypass bit also depends on "enabled". > + * Period is allowed to be rounded up or down. > + */ > + clk_rate = clk_get_rate(sun4i_pwm->clk); > + bypass = ((state->period * clk_rate >= NSEC_PER_SEC && > + state->period * clk_rate < NSEC_PER_SEC + clk_rate) && > + state->enabled); I guess the compiler is smart enough here, but checking for state->enabled is cheaper than the other checks, so putting this at the start of the expression seems sensible. The comment doesn't match the code. You don't round up state->period. (This is good, please fix the comment.) I think dropping the check state->period * clk_rate < NSEC_PER_SEC + clk_rate would be fine, too. I'd like to have a check for state->duty_cycle * clk_rate >= NSEC_PER_SEC / 2 && state->duty_cycle * clk_rate < NSEC_PER_SEC here. If this isn't true rather disable the PWM or output a 100% duty cycle with a larger period. > + > spin_lock(&sun4i_pwm->ctrl_lock); > ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG); > Best regards Uwe -- Pengutronix e.K. | Uwe Kleine-König | Industrial Linux Solutions | http://www.pengutronix.de/ | _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2019-11-04 8:38 UTC|newest] Thread overview: 71+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-11-03 20:33 [PATCH v2 0/7] Add support for H6 PWM Clément Péron 2019-11-03 20:33 ` Clément Péron 2019-11-03 20:33 ` [PATCH v2 1/7] dt-bindings: pwm: allwinner: Add H6 PWM description Clément Péron 2019-11-03 20:33 ` Clément Péron 2019-11-04 8:03 ` Uwe Kleine-König 2019-11-04 8:03 ` Uwe Kleine-König 2019-11-04 17:49 ` Clément Péron 2019-11-04 17:49 ` Clément Péron 2019-11-05 11:11 ` Maxime Ripard 2019-11-05 11:11 ` Maxime Ripard 2019-11-05 12:34 ` Clément Péron 2019-11-05 12:34 ` Clément Péron 2019-11-05 17:32 ` Maxime Ripard 2019-11-05 17:32 ` Maxime Ripard 2019-11-06 9:25 ` Clément Péron 2019-11-06 9:25 ` Clément Péron 2019-11-03 20:33 ` [PATCH v2 2/7] pwm: sun4i: Add an optional probe for reset line Clément Péron 2019-11-03 20:33 ` Clément Péron 2019-11-04 8:11 ` Uwe Kleine-König 2019-11-04 8:11 ` Uwe Kleine-König 2019-11-04 17:50 ` Clément Péron 2019-11-04 17:50 ` Clément Péron 2019-11-05 7:01 ` Philipp Zabel 2019-11-05 7:01 ` Philipp Zabel 2019-11-05 13:03 ` Clément Péron 2019-11-05 13:03 ` Clément Péron 2019-11-03 20:33 ` [PATCH v2 3/7] pwm: sun4i: Add an optional probe for bus clock Clément Péron 2019-11-03 20:33 ` Clément Péron 2019-11-04 8:24 ` Uwe Kleine-König 2019-11-04 8:24 ` Uwe Kleine-König 2019-11-04 18:07 ` Clément Péron 2019-11-04 18:07 ` Clément Péron 2019-11-04 20:10 ` Uwe Kleine-König 2019-11-04 20:10 ` Uwe Kleine-König 2019-11-04 20:10 ` Uwe Kleine-König 2019-11-04 20:19 ` Jernej Škrabec 2019-11-04 20:19 ` Jernej Škrabec 2019-11-04 20:27 ` Clément Péron 2019-11-04 20:27 ` Clément Péron 2019-11-04 20:38 ` Jernej Škrabec 2019-11-04 20:38 ` Jernej Škrabec 2019-11-03 20:33 ` [PATCH v2 4/7] pwm: sun4i: Add support to output source clock directly Clément Péron 2019-11-03 20:33 ` Clément Péron 2019-11-03 22:30 ` kbuild test robot 2019-11-03 22:30 ` kbuild test robot 2019-11-03 22:30 ` kbuild test robot 2019-11-03 22:30 ` kbuild test robot 2019-11-03 22:41 ` Clément Péron 2019-11-03 22:41 ` Clément Péron 2019-11-03 22:58 ` kbuild test robot 2019-11-03 22:58 ` kbuild test robot 2019-11-03 22:58 ` kbuild test robot 2019-11-03 22:58 ` kbuild test robot 2019-11-04 8:38 ` Uwe Kleine-König [this message] 2019-11-04 8:38 ` Uwe Kleine-König 2019-11-04 21:28 ` Clément Péron 2019-11-04 21:28 ` Clément Péron 2019-11-05 7:29 ` Uwe Kleine-König 2019-11-05 7:29 ` Uwe Kleine-König 2019-11-05 12:58 ` Clément Péron 2019-11-05 12:58 ` Clément Péron 2019-11-05 13:12 ` Uwe Kleine-König 2019-11-05 13:12 ` Uwe Kleine-König 2019-11-05 13:12 ` Clément Péron 2019-11-05 13:12 ` Clément Péron 2019-11-03 20:33 ` [PATCH v2 5/7] pwm: sun4i: Add support for H6 PWM Clément Péron 2019-11-03 20:33 ` Clément Péron 2019-11-03 20:33 ` [PATCH v2 6/7] arm64: dts: allwinner: h6: Add PWM node Clément Péron 2019-11-03 20:33 ` Clément Péron 2019-11-03 20:33 ` [PATCH v2 7/7] [DO NOT MERGE] arm64: allwinner: h6: enable Beelink GS1 PWM Clément Péron 2019-11-03 20:33 ` Clément Péron
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