From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Mark Brown <broonie@kernel.org>
Cc: Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com>,
Tudor Ambarus <Tudor.Ambarus@microchip.com>,
Michal Simek <michal.simek@xilinx.com>,
linux-spi@vger.kernel.org,
Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 1/7] spi: zynq-qspi: Anything else than CS0 is not supported yet
Date: Fri, 8 Nov 2019 14:31:34 +0100 [thread overview]
Message-ID: <20191108143134.1490f092@xps13> (raw)
In-Reply-To: <20191108120732.GB5532@sirena.co.uk>
Hi Mark,
Mark Brown <broonie@kernel.org> wrote on Fri, 8 Nov 2019 12:07:32 +0000:
> On Fri, Nov 08, 2019 at 11:59:14AM +0100, Miquel Raynal wrote:
> > Unlike what the driver is currently advertizing, CS0 only can be used,
> > CS1 is not supported at all. Prevent people to use CS1.
>
> This (and the rest of the series) doesn't apply against current code,
> please check and resend.
My bad, I thought I was working on a v5.3 while I was on a v5.1. Let me
rebase and resend the whole patchset. Sorry for the mistake.
Thanks,
Miquèl
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next prev parent reply other threads:[~2019-11-08 13:31 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-08 10:59 [PATCH 0/7] spi: zynq-qspi: Clarify and fix the chip selection Miquel Raynal
2019-11-08 10:59 ` [PATCH 1/7] spi: zynq-qspi: Anything else than CS0 is not supported yet Miquel Raynal
2019-11-08 10:59 ` Miquel Raynal
2019-11-08 12:07 ` Mark Brown
2019-11-08 13:31 ` Miquel Raynal [this message]
2019-11-08 10:59 ` [PATCH 2/7] spi: zynq-qspi: Keep the naming consistent across the driver Miquel Raynal
2019-11-08 10:59 ` Miquel Raynal
2019-11-08 12:08 ` Applied "spi: zynq-qspi: Keep the naming consistent across the driver" to the spi tree Mark Brown
2019-11-08 12:08 ` Mark Brown
2019-11-08 10:59 ` [PATCH 3/7] spi: zynq-qspi: Keep the bitfields naming consistent Miquel Raynal
2019-11-08 10:59 ` Miquel Raynal
2019-11-08 10:59 ` [PATCH 4/7] spi: zynq-qspi: Enhance the Linear CFG bit definitions Miquel Raynal
2019-11-08 10:59 ` Miquel Raynal
2019-11-08 10:59 ` [PATCH 5/7] spi: zynq-qspi: Clarify the select chip function Miquel Raynal
2019-11-08 10:59 ` Miquel Raynal
2019-11-08 10:59 ` [PATCH 6/7] spi: zynq-qspi: Do the actual hardware initialization later in the probe Miquel Raynal
2019-11-08 10:59 ` Miquel Raynal
2019-11-08 10:59 ` [PATCH 7/7] spi: zynq-qspi: Support two chip selects Miquel Raynal
2019-11-08 10:59 ` Miquel Raynal
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