From: Marc Zyngier <maz@kernel.org> To: kvmarm@lists.cs.columbia.edu, linux-kernel@vger.kernel.org Cc: Eric Auger <eric.auger@redhat.com>, James Morse <james.morse@arm.com>, Julien Thierry <julien.thierry.kdev@gmail.com>, Suzuki K Poulose <suzuki.poulose@arm.com>, Thomas Gleixner <tglx@linutronix.de>, Jason Cooper <jason@lakedaemon.net>, Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>, Andrew Murray <Andrew.Murray@arm.com>, Zenghui Yu <yuzenghui@huawei.com>, Robert Richter <rrichter@marvell.com> Subject: [PATCH v3 02/32] irqchip/gic-v3: Add GICv4.1 VPEID size discovery Date: Tue, 24 Dec 2019 11:10:25 +0000 [thread overview] Message-ID: <20191224111055.11836-3-maz@kernel.org> (raw) In-Reply-To: <20191224111055.11836-1-maz@kernel.org> While GICv4.0 mandates 16 bit worth of VPEIDs, GICv4.1 allows smaller implementations to be built. Add the required glue to dynamically compute the limit. Reviewed-by: Zenghui Yu <yuzenghui@huawei.com> Signed-off-by: Marc Zyngier <maz@kernel.org> --- drivers/irqchip/irq-gic-v3-its.c | 11 ++++++++++- drivers/irqchip/irq-gic-v3.c | 3 +++ include/linux/irqchip/arm-gic-v3.h | 5 +++++ 3 files changed, 18 insertions(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index e05673bcd52b..d9d256471dc0 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -121,7 +121,16 @@ struct its_node { #define ITS_ITT_ALIGN SZ_256 /* The maximum number of VPEID bits supported by VLPI commands */ -#define ITS_MAX_VPEID_BITS (16) +#define ITS_MAX_VPEID_BITS \ + ({ \ + int nvpeid = 16; \ + if (gic_rdists->has_rvpeid && \ + gic_rdists->gicd_typer2 & GICD_TYPER2_VIL) \ + nvpeid = 1 + (gic_rdists->gicd_typer2 & \ + GICD_TYPER2_VID); \ + \ + nvpeid; \ + }) #define ITS_MAX_VPEID (1 << (ITS_MAX_VPEID_BITS)) /* Convert page order to size in bytes */ diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index ffcb018395ed..286f98222878 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -1576,6 +1576,9 @@ static int __init gic_init_bases(void __iomem *dist_base, pr_info("%d SPIs implemented\n", GIC_LINE_NR - 32); pr_info("%d Extended SPIs implemented\n", GIC_ESPI_NR); + + gic_data.rdists.gicd_typer2 = readl_relaxed(gic_data.dist_base + GICD_TYPER2); + gic_data.domain = irq_domain_create_tree(handle, &gic_irq_domain_ops, &gic_data); irq_domain_update_bus_token(gic_data.domain, DOMAIN_BUS_WIRED); diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h index 9a5f85d30701..9dfe64189d99 100644 --- a/include/linux/irqchip/arm-gic-v3.h +++ b/include/linux/irqchip/arm-gic-v3.h @@ -13,6 +13,7 @@ #define GICD_CTLR 0x0000 #define GICD_TYPER 0x0004 #define GICD_IIDR 0x0008 +#define GICD_TYPER2 0x000C #define GICD_STATUSR 0x0010 #define GICD_SETSPI_NSR 0x0040 #define GICD_CLRSPI_NSR 0x0048 @@ -89,6 +90,9 @@ #define GICD_TYPER_ESPIS(typer) \ (((typer) & GICD_TYPER_ESPI) ? GICD_TYPER_SPIS((typer) >> 27) : 0) +#define GICD_TYPER2_VIL (1U << 7) +#define GICD_TYPER2_VID GENMASK(4, 0) + #define GICD_IROUTER_SPI_MODE_ONE (0U << 31) #define GICD_IROUTER_SPI_MODE_ANY (1U << 31) @@ -615,6 +619,7 @@ struct rdists { void *prop_table_va; u64 flags; u32 gicd_typer; + u32 gicd_typer2; bool has_vlpis; bool has_rvpeid; bool has_direct_lpi; -- 2.20.1
WARNING: multiple messages have this Message-ID (diff)
From: Marc Zyngier <maz@kernel.org> To: kvmarm@lists.cs.columbia.edu, linux-kernel@vger.kernel.org Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>, Jason Cooper <jason@lakedaemon.net>, Robert Richter <rrichter@marvell.com>, Thomas Gleixner <tglx@linutronix.de> Subject: [PATCH v3 02/32] irqchip/gic-v3: Add GICv4.1 VPEID size discovery Date: Tue, 24 Dec 2019 11:10:25 +0000 [thread overview] Message-ID: <20191224111055.11836-3-maz@kernel.org> (raw) In-Reply-To: <20191224111055.11836-1-maz@kernel.org> While GICv4.0 mandates 16 bit worth of VPEIDs, GICv4.1 allows smaller implementations to be built. Add the required glue to dynamically compute the limit. Reviewed-by: Zenghui Yu <yuzenghui@huawei.com> Signed-off-by: Marc Zyngier <maz@kernel.org> --- drivers/irqchip/irq-gic-v3-its.c | 11 ++++++++++- drivers/irqchip/irq-gic-v3.c | 3 +++ include/linux/irqchip/arm-gic-v3.h | 5 +++++ 3 files changed, 18 insertions(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index e05673bcd52b..d9d256471dc0 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -121,7 +121,16 @@ struct its_node { #define ITS_ITT_ALIGN SZ_256 /* The maximum number of VPEID bits supported by VLPI commands */ -#define ITS_MAX_VPEID_BITS (16) +#define ITS_MAX_VPEID_BITS \ + ({ \ + int nvpeid = 16; \ + if (gic_rdists->has_rvpeid && \ + gic_rdists->gicd_typer2 & GICD_TYPER2_VIL) \ + nvpeid = 1 + (gic_rdists->gicd_typer2 & \ + GICD_TYPER2_VID); \ + \ + nvpeid; \ + }) #define ITS_MAX_VPEID (1 << (ITS_MAX_VPEID_BITS)) /* Convert page order to size in bytes */ diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index ffcb018395ed..286f98222878 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -1576,6 +1576,9 @@ static int __init gic_init_bases(void __iomem *dist_base, pr_info("%d SPIs implemented\n", GIC_LINE_NR - 32); pr_info("%d Extended SPIs implemented\n", GIC_ESPI_NR); + + gic_data.rdists.gicd_typer2 = readl_relaxed(gic_data.dist_base + GICD_TYPER2); + gic_data.domain = irq_domain_create_tree(handle, &gic_irq_domain_ops, &gic_data); irq_domain_update_bus_token(gic_data.domain, DOMAIN_BUS_WIRED); diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h index 9a5f85d30701..9dfe64189d99 100644 --- a/include/linux/irqchip/arm-gic-v3.h +++ b/include/linux/irqchip/arm-gic-v3.h @@ -13,6 +13,7 @@ #define GICD_CTLR 0x0000 #define GICD_TYPER 0x0004 #define GICD_IIDR 0x0008 +#define GICD_TYPER2 0x000C #define GICD_STATUSR 0x0010 #define GICD_SETSPI_NSR 0x0040 #define GICD_CLRSPI_NSR 0x0048 @@ -89,6 +90,9 @@ #define GICD_TYPER_ESPIS(typer) \ (((typer) & GICD_TYPER_ESPI) ? GICD_TYPER_SPIS((typer) >> 27) : 0) +#define GICD_TYPER2_VIL (1U << 7) +#define GICD_TYPER2_VID GENMASK(4, 0) + #define GICD_IROUTER_SPI_MODE_ONE (0U << 31) #define GICD_IROUTER_SPI_MODE_ANY (1U << 31) @@ -615,6 +619,7 @@ struct rdists { void *prop_table_va; u64 flags; u32 gicd_typer; + u32 gicd_typer2; bool has_vlpis; bool has_rvpeid; bool has_direct_lpi; -- 2.20.1 _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
next prev parent reply other threads:[~2019-12-24 11:11 UTC|newest] Thread overview: 119+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-12-24 11:10 [PATCH v3 00/32] irqchip/gic-v4: GICv4.1 architecture support Marc Zyngier 2019-12-24 11:10 ` Marc Zyngier 2019-12-24 11:10 ` [PATCH v3 01/32] irqchip/gic-v3: Detect GICv4.1 supporting RVPEID Marc Zyngier 2019-12-24 11:10 ` Marc Zyngier 2020-01-24 19:11 ` [tip: irq/core] " tip-bot2 for Marc Zyngier 2019-12-24 11:10 ` Marc Zyngier [this message] 2019-12-24 11:10 ` [PATCH v3 02/32] irqchip/gic-v3: Add GICv4.1 VPEID size discovery Marc Zyngier 2020-01-24 19:11 ` [tip: irq/core] " tip-bot2 for Marc Zyngier 2019-12-24 11:10 ` [PATCH v3 03/32] irqchip/gic-v3: Workaround Cavium TX1 erratum when reading GICD_TYPER2 Marc Zyngier 2019-12-24 11:10 ` Marc Zyngier 2020-03-09 22:11 ` Robert Richter 2020-03-09 22:11 ` Robert Richter 2020-03-10 11:41 ` Marc Zyngier 2020-03-10 11:41 ` Marc Zyngier 2020-03-10 12:34 ` Robert Richter 2020-03-10 12:34 ` Robert Richter 2020-03-11 8:45 ` Robert Richter 2020-03-11 8:45 ` Robert Richter 2020-03-11 9:03 ` Marc Zyngier 2020-03-11 9:03 ` Marc Zyngier 2020-03-11 9:18 ` Robert Richter 2020-03-11 9:18 ` Robert Richter 2019-12-24 11:10 ` [PATCH v3 04/32] irqchip/gic-v3: Use SGIs without active state if offered Marc Zyngier 2019-12-24 11:10 ` Marc Zyngier 2019-12-28 8:56 ` Zenghui Yu 2019-12-28 8:56 ` Zenghui Yu 2019-12-28 10:36 ` Marc Zyngier 2019-12-28 10:36 ` Marc Zyngier 2019-12-30 3:50 ` Zenghui Yu 2019-12-30 3:50 ` Zenghui Yu 2019-12-24 11:10 ` [PATCH v3 05/32] irqchip/gic-v4.1: VPE table (aka GICR_VPROPBASER) allocation Marc Zyngier 2019-12-24 11:10 ` Marc Zyngier 2020-01-20 14:03 ` Zenghui Yu 2020-01-20 14:03 ` Zenghui Yu 2020-01-20 15:11 ` Marc Zyngier 2020-01-20 15:11 ` Marc Zyngier 2020-01-22 2:59 ` Zenghui Yu 2020-01-22 2:59 ` Zenghui Yu 2020-01-24 19:11 ` [tip: irq/core] " tip-bot2 for Marc Zyngier 2019-12-24 11:10 ` [PATCH v3 06/32] irqchip/gic-v4.1: Implement the v4.1 flavour of VMAPP Marc Zyngier 2019-12-24 11:10 ` Marc Zyngier 2020-01-24 19:11 ` [tip: irq/core] " tip-bot2 for Marc Zyngier 2019-12-24 11:10 ` [PATCH v3 07/32] irqchip/gic-v4.1: Don't use the VPE proxy if RVPEID is set Marc Zyngier 2019-12-24 11:10 ` Marc Zyngier 2020-01-24 19:11 ` [tip: irq/core] " tip-bot2 for Marc Zyngier 2019-12-24 11:10 ` [PATCH v3 08/32] irqchip/gic-v4.1: Implement the v4.1 flavour of VMOVP Marc Zyngier 2019-12-24 11:10 ` Marc Zyngier 2020-01-24 19:11 ` [tip: irq/core] " tip-bot2 for Marc Zyngier 2019-12-24 11:10 ` [PATCH v3 09/32] irqchip/gic-v4.1: Plumb skeletal VPE irqchip Marc Zyngier 2019-12-24 11:10 ` Marc Zyngier 2020-01-24 19:11 ` [tip: irq/core] " tip-bot2 for Marc Zyngier 2019-12-24 11:10 ` [PATCH v3 10/32] irqchip/gic-v4.1: Add mask/unmask doorbell callbacks Marc Zyngier 2019-12-24 11:10 ` Marc Zyngier 2020-01-24 19:11 ` [tip: irq/core] " tip-bot2 for Marc Zyngier 2019-12-24 11:10 ` [PATCH v3 11/32] irqchip/gic-v4.1: Add VPE residency callback Marc Zyngier 2019-12-24 11:10 ` Marc Zyngier 2020-01-24 19:11 ` [tip: irq/core] " tip-bot2 for Marc Zyngier 2019-12-24 11:10 ` [PATCH v3 12/32] irqchip/gic-v4.1: Add VPE eviction callback Marc Zyngier 2019-12-24 11:10 ` Marc Zyngier 2020-01-24 19:11 ` [tip: irq/core] " tip-bot2 for Marc Zyngier 2019-12-24 11:10 ` [PATCH v3 13/32] irqchip/gic-v4.1: Add VPE INVALL callback Marc Zyngier 2019-12-24 11:10 ` Marc Zyngier 2020-01-24 19:11 ` [tip: irq/core] " tip-bot2 for Marc Zyngier 2019-12-24 11:10 ` [PATCH v3 14/32] irqchip/gic-v4.1: Suppress per-VLPI doorbell Marc Zyngier 2019-12-24 11:10 ` Marc Zyngier 2020-01-24 19:11 ` [tip: irq/core] " tip-bot2 for Marc Zyngier 2019-12-24 11:10 ` [PATCH v3 15/32] irqchip/gic-v4.1: Allow direct invalidation of VLPIs Marc Zyngier 2019-12-24 11:10 ` Marc Zyngier 2020-01-24 19:11 ` [tip: irq/core] " tip-bot2 for Marc Zyngier 2019-12-24 11:10 ` [PATCH v3 16/32] irqchip/gic-v4.1: Advertise support v4.1 to KVM Marc Zyngier 2019-12-24 11:10 ` Marc Zyngier 2019-12-24 11:10 ` [PATCH v3 17/32] irqchip/gic-v4.1: Map the ITS SGIR register page Marc Zyngier 2019-12-24 11:10 ` Marc Zyngier 2019-12-24 11:10 ` [PATCH v3 18/32] irqchip/gic-v4.1: Plumb skeletal VSGI irqchip Marc Zyngier 2019-12-24 11:10 ` Marc Zyngier 2019-12-24 11:10 ` [PATCH v3 19/32] irqchip/gic-v4.1: Add initial SGI configuration Marc Zyngier 2019-12-24 11:10 ` Marc Zyngier 2019-12-24 11:10 ` [PATCH v3 20/32] irqchip/gic-v4.1: Plumb mask/unmask SGI callbacks Marc Zyngier 2019-12-24 11:10 ` Marc Zyngier 2019-12-24 11:10 ` [PATCH v3 21/32] irqchip/gic-v4.1: Plumb get/set_irqchip_state " Marc Zyngier 2019-12-24 11:10 ` Marc Zyngier 2019-12-24 11:10 ` [PATCH v3 22/32] irqchip/gic-v4.1: Plumb set_vcpu_affinity " Marc Zyngier 2019-12-24 11:10 ` Marc Zyngier 2019-12-24 11:10 ` [PATCH v3 23/32] irqchip/gic-v4.1: Move doorbell management to the GICv4 abstraction layer Marc Zyngier 2019-12-24 11:10 ` Marc Zyngier 2019-12-24 11:10 ` [PATCH v3 24/32] irqchip/gic-v4.1: Add VSGI allocation/teardown Marc Zyngier 2019-12-24 11:10 ` Marc Zyngier 2019-12-24 11:10 ` [PATCH v3 25/32] irqchip/gic-v4.1: Add VSGI property setup Marc Zyngier 2019-12-24 11:10 ` Marc Zyngier 2019-12-24 11:10 ` [PATCH v3 26/32] irqchip/gic-v4.1: Eagerly vmap vPEs Marc Zyngier 2019-12-24 11:10 ` Marc Zyngier 2019-12-24 11:10 ` [PATCH v3 27/32] KVM: arm64: GICv4.1: Let doorbells be auto-enabled Marc Zyngier 2019-12-24 11:10 ` Marc Zyngier 2019-12-24 11:10 ` [PATCH v3 28/32] KVM: arm64: GICv4.1: Add direct injection capability to SGI registers Marc Zyngier 2019-12-24 11:10 ` Marc Zyngier 2019-12-28 9:19 ` Zenghui Yu 2019-12-28 9:19 ` Zenghui Yu 2019-12-28 10:41 ` Marc Zyngier 2019-12-28 10:41 ` Marc Zyngier 2019-12-24 11:10 ` [PATCH v3 29/32] KVM: arm64: GICv4.1: Allow SGIs to switch between HW and SW interrupts Marc Zyngier 2019-12-24 11:10 ` Marc Zyngier 2020-01-15 2:49 ` Shaokun Zhang 2020-01-15 2:49 ` Shaokun Zhang 2020-01-15 3:49 ` Zenghui Yu 2020-01-15 3:49 ` Zenghui Yu 2020-01-15 13:32 ` Marc Zyngier 2020-01-15 13:32 ` Marc Zyngier 2020-01-15 13:49 ` Zenghui Yu 2020-01-15 13:49 ` Zenghui Yu 2020-01-16 6:13 ` Shaokun Zhang 2020-01-16 6:13 ` Shaokun Zhang 2020-01-15 13:17 ` Marc Zyngier 2020-01-15 13:17 ` Marc Zyngier 2019-12-24 11:10 ` [PATCH v3 30/32] KVM: arm64: GICv4.1: Plumb SGI implementation selection in the distributor Marc Zyngier 2019-12-24 11:10 ` Marc Zyngier 2019-12-24 11:10 ` [PATCH v3 31/32] KVM: arm64: GICv4.1: Reload VLPI configuration on distributor enable/disable Marc Zyngier 2019-12-24 11:10 ` Marc Zyngier 2019-12-24 11:10 ` [PATCH v3 32/32] KVM: arm64: GICv4.1: Expose HW-based SGIs in debugfs Marc Zyngier 2019-12-24 11:10 ` Marc Zyngier
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