From: Bjorn Andersson <bjorn.andersson@linaro.org>
To: Douglas Anderson <dianders@chromium.org>
Cc: Andrzej Hajda <a.hajda@samsung.com>,
Neil Armstrong <narmstrong@baylibre.com>,
robdclark@chromium.org, linux-arm-msm@vger.kernel.org,
seanpaul@chromium.org, Jeffrey Hugo <jeffrey.l.hugo@gmail.com>,
Daniel Vetter <daniel@ffwll.ch>, Rob Clark <robdclark@gmail.com>,
Jonas Karlman <jonas@kwiboo.se>,
linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
David Airlie <airlied@linux.ie>,
Jernej Skrabec <jernej.skrabec@siol.net>,
Laurent Pinchart <Laurent.pinchart@ideasonboard.com>
Subject: Re: [PATCH v3 4/9] drm/bridge: ti-sn65dsi86: Config number of DP lanes Mo' Betta
Date: Mon, 3 Feb 2020 15:34:21 -0800 [thread overview]
Message-ID: <20200203233421.GD311651@builder> (raw)
In-Reply-To: <20191218143416.v3.4.If3e2d0493e7b6e8b510ea90d8724ff760379b3ba@changeid>
On Wed 18 Dec 14:35 PST 2019, Douglas Anderson wrote:
> The driver used to say that the value to program into bridge register
> 0x93 was dp_lanes - 1. Looking at the datasheet for the bridge, this
> is wrong. The data sheet says:
> * 1 = 1 lane
> * 2 = 2 lanes
> * 3 = 4 lanes
>
> A more proper way to express this encoding is min(dp_lanes, 3).
>
> At the moment this change has zero effect because we've hardcoded the
> number of DP lanes to 4. ...and (4 - 1) == min(4, 3). How fortunate!
> ...but soon we'll stop hardcoding the number of lanes.
>
> Signed-off-by: Douglas Anderson <dianders@chromium.org>
> Tested-by: Rob Clark <robdclark@gmail.com>
> Reviewed-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> ---
>
> Changes in v3: None
> Changes in v2: None
>
> drivers/gpu/drm/bridge/ti-sn65dsi86.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge/ti-sn65dsi86.c
> index ab644baaf90c..d55d19759796 100644
> --- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c
> +++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c
> @@ -523,7 +523,7 @@ static void ti_sn_bridge_enable(struct drm_bridge *bridge)
> CHA_DSI_LANES_MASK, val);
>
> /* DP lane config */
> - val = DP_NUM_LANES(pdata->dp_lanes - 1);
> + val = DP_NUM_LANES(min(pdata->dp_lanes, 3));
> regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK,
> val);
>
> --
> 2.24.1.735.g03f4e72817-goog
>
WARNING: multiple messages have this Message-ID (diff)
From: Bjorn Andersson <bjorn.andersson@linaro.org>
To: Douglas Anderson <dianders@chromium.org>
Cc: robdclark@chromium.org, Jernej Skrabec <jernej.skrabec@siol.net>,
Jeffrey Hugo <jeffrey.l.hugo@gmail.com>,
David Airlie <airlied@linux.ie>,
linux-arm-msm@vger.kernel.org,
Neil Armstrong <narmstrong@baylibre.com>,
linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
Andrzej Hajda <a.hajda@samsung.com>,
seanpaul@chromium.org,
Laurent Pinchart <Laurent.pinchart@ideasonboard.com>,
Jonas Karlman <jonas@kwiboo.se>
Subject: Re: [PATCH v3 4/9] drm/bridge: ti-sn65dsi86: Config number of DP lanes Mo' Betta
Date: Mon, 3 Feb 2020 15:34:21 -0800 [thread overview]
Message-ID: <20200203233421.GD311651@builder> (raw)
In-Reply-To: <20191218143416.v3.4.If3e2d0493e7b6e8b510ea90d8724ff760379b3ba@changeid>
On Wed 18 Dec 14:35 PST 2019, Douglas Anderson wrote:
> The driver used to say that the value to program into bridge register
> 0x93 was dp_lanes - 1. Looking at the datasheet for the bridge, this
> is wrong. The data sheet says:
> * 1 = 1 lane
> * 2 = 2 lanes
> * 3 = 4 lanes
>
> A more proper way to express this encoding is min(dp_lanes, 3).
>
> At the moment this change has zero effect because we've hardcoded the
> number of DP lanes to 4. ...and (4 - 1) == min(4, 3). How fortunate!
> ...but soon we'll stop hardcoding the number of lanes.
>
> Signed-off-by: Douglas Anderson <dianders@chromium.org>
> Tested-by: Rob Clark <robdclark@gmail.com>
> Reviewed-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> ---
>
> Changes in v3: None
> Changes in v2: None
>
> drivers/gpu/drm/bridge/ti-sn65dsi86.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge/ti-sn65dsi86.c
> index ab644baaf90c..d55d19759796 100644
> --- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c
> +++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c
> @@ -523,7 +523,7 @@ static void ti_sn_bridge_enable(struct drm_bridge *bridge)
> CHA_DSI_LANES_MASK, val);
>
> /* DP lane config */
> - val = DP_NUM_LANES(pdata->dp_lanes - 1);
> + val = DP_NUM_LANES(min(pdata->dp_lanes, 3));
> regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK,
> val);
>
> --
> 2.24.1.735.g03f4e72817-goog
>
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next prev parent reply other threads:[~2020-02-03 23:34 UTC|newest]
Thread overview: 74+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-12-18 22:35 [PATCH v3 0/9] drm/bridge: ti-sn65dsi86: Improve support for AUO B116XAK01 + other DP Douglas Anderson
2019-12-18 22:35 ` Douglas Anderson
2019-12-18 22:35 ` [PATCH v3 1/9] drm/bridge: ti-sn65dsi86: Split the setting of the dp and dsi rates Douglas Anderson
2019-12-18 22:35 ` Douglas Anderson
2020-02-03 23:31 ` Bjorn Andersson
2020-02-03 23:31 ` Bjorn Andersson
2019-12-18 22:35 ` [PATCH v3 2/9] drm/bridge: ti-sn65dsi86: zero is never greater than an unsigned int Douglas Anderson
2019-12-18 22:35 ` Douglas Anderson
2020-02-03 23:32 ` Bjorn Andersson
2020-02-03 23:32 ` Bjorn Andersson
2019-12-18 22:35 ` [PATCH v3 3/9] drm/bridge: ti-sn65dsi86: Don't use MIPI variables for DP link Douglas Anderson
2019-12-18 22:35 ` Douglas Anderson
2020-02-03 23:33 ` Bjorn Andersson
2020-02-03 23:33 ` Bjorn Andersson
2019-12-18 22:35 ` [PATCH v3 4/9] drm/bridge: ti-sn65dsi86: Config number of DP lanes Mo' Betta Douglas Anderson
2019-12-18 22:35 ` Douglas Anderson
2020-02-03 23:34 ` Bjorn Andersson [this message]
2020-02-03 23:34 ` Bjorn Andersson
2019-12-18 22:35 ` [PATCH v3 5/9] drm/bridge: ti-sn65dsi86: Read num lanes from the DP sink Douglas Anderson
2019-12-18 22:35 ` Douglas Anderson
2020-02-03 23:35 ` Bjorn Andersson
2020-02-03 23:35 ` Bjorn Andersson
2019-12-18 22:35 ` [PATCH v3 6/9] drm/bridge: ti-sn65dsi86: Use 18-bit DP if we can Douglas Anderson
2019-12-18 22:35 ` Douglas Anderson
2020-02-03 23:37 ` Bjorn Andersson
2020-02-03 23:37 ` Bjorn Andersson
2020-02-04 0:21 ` Doug Anderson
2020-02-04 0:21 ` Doug Anderson
2020-02-12 23:04 ` Doug Anderson
2020-02-12 23:04 ` Doug Anderson
2020-02-13 9:17 ` Neil Armstrong
2020-02-13 9:17 ` Neil Armstrong
[not found] ` <20200710011935.GA7056@gentoo.org>
2020-07-10 1:38 ` Doug Anderson
2020-07-10 1:38 ` Doug Anderson
2020-07-10 2:14 ` Doug Anderson
2020-07-10 2:14 ` Doug Anderson
2020-07-10 3:12 ` Steev Klimaszewski
2020-07-10 3:12 ` Steev Klimaszewski
2020-07-10 3:17 ` Steev Klimaszewski
2020-07-10 3:17 ` Steev Klimaszewski
2020-07-10 3:43 ` Steev Klimaszewski
2020-07-10 3:43 ` Steev Klimaszewski
2020-07-10 4:12 ` Doug Anderson
2020-07-10 4:12 ` Doug Anderson
2020-07-10 6:15 ` Steev Klimaszewski
2020-07-10 6:15 ` Steev Klimaszewski
2020-07-10 14:16 ` Rob Clark
2020-07-10 14:16 ` Rob Clark
2020-07-10 14:47 ` Doug Anderson
2020-07-10 14:47 ` Doug Anderson
2020-07-10 17:10 ` Steev Klimaszewski
2020-07-10 17:10 ` Steev Klimaszewski
2020-07-14 15:31 ` Doug Anderson
2020-07-14 15:31 ` Doug Anderson
2020-09-02 14:37 ` Doug Anderson
2020-09-02 14:37 ` Doug Anderson
2019-12-18 22:35 ` [PATCH v3 7/9] drm/bridge: ti-sn65dsi86: Group DP link training bits in a function Douglas Anderson
2019-12-18 22:35 ` Douglas Anderson
2020-02-03 23:39 ` Bjorn Andersson
2020-02-03 23:39 ` Bjorn Andersson
2019-12-18 22:35 ` [PATCH v3 8/9] drm/bridge: ti-sn65dsi86: Train at faster rates if slower ones fail Douglas Anderson
2019-12-18 22:35 ` Douglas Anderson
2020-02-03 23:41 ` Bjorn Andersson
2020-02-03 23:41 ` Bjorn Andersson
2019-12-18 22:35 ` [PATCH v3 9/9] drm/bridge: ti-sn65dsi86: Avoid invalid rates Douglas Anderson
2019-12-18 22:35 ` Douglas Anderson
2020-02-03 23:43 ` Bjorn Andersson
2020-02-03 23:43 ` Bjorn Andersson
2020-01-06 22:47 ` [PATCH v3 0/9] drm/bridge: ti-sn65dsi86: Improve support for AUO B116XAK01 + other DP Doug Anderson
2020-01-06 22:47 ` Doug Anderson
2020-02-03 23:45 ` Bjorn Andersson
2020-02-03 23:45 ` Bjorn Andersson
2020-02-13 9:51 ` Neil Armstrong
2020-02-13 9:51 ` Neil Armstrong
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