From: Andre Przywara <andre.przywara@arm.com> To: "David S . Miller" <davem@davemloft.net>, Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Cc: Michal Simek <michal.simek@xilinx.com>, Robert Hancock <hancock@sedsystems.ca>, netdev@vger.kernel.org, rmk+kernel@arm.linux.org.uk, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Andrew Lunn <andrew@lunn.ch> Subject: [PATCH v2 13/14] net: axienet: Autodetect 64-bit DMA capability Date: Mon, 9 Mar 2020 18:18:50 +0000 [thread overview] Message-ID: <20200309181851.190164-14-andre.przywara@arm.com> (raw) In-Reply-To: <20200309181851.190164-1-andre.przywara@arm.com> When newer revisions of the Axienet IP are configured for a 64-bit bus, we *need* to write to the MSB part of the an address registers, otherwise the IP won't recognise this as a DMA start condition. This is even true when the actual DMA address comes from the lower 4 GB. To autodetect this configuration, at probe time we write all 1's to such an MSB register, and see if any bits stick. If this is configured for a 32-bit bus, those MSB registers are RES0, so reading back 0 indicates that no MSB writes are necessary. On the other hands reading anything other than 0 indicated the need to write the MSB registers, so we set the respective flag. The actual DMA mask stays at 32-bit for now. To help bisecting, a separate patch will enable allocations from higher addresses. Signed-off-by: Andre Przywara <andre.przywara@arm.com> --- drivers/net/ethernet/xilinx/xilinx_axienet.h | 1 + .../net/ethernet/xilinx/xilinx_axienet_main.c | 26 +++++++++++++++++++ 2 files changed, 27 insertions(+) diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet.h b/drivers/net/ethernet/xilinx/xilinx_axienet.h index 84c4c3655516..fbaf3c987d9c 100644 --- a/drivers/net/ethernet/xilinx/xilinx_axienet.h +++ b/drivers/net/ethernet/xilinx/xilinx_axienet.h @@ -161,6 +161,7 @@ #define XAE_FCC_OFFSET 0x0000040C /* Flow Control Configuration */ #define XAE_EMMC_OFFSET 0x00000410 /* EMAC mode configuration */ #define XAE_PHYC_OFFSET 0x00000414 /* RGMII/SGMII configuration */ +#define XAE_ID_OFFSET 0x000004F8 /* Identification register */ #define XAE_MDIO_MC_OFFSET 0x00000500 /* MII Management Config */ #define XAE_MDIO_MCR_OFFSET 0x00000504 /* MII Management Control */ #define XAE_MDIO_MWD_OFFSET 0x00000508 /* MII Management Write Data */ diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c index edee0666d52c..8c0887b1c009 100644 --- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c +++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c @@ -151,6 +151,9 @@ static void axienet_dma_out_addr(struct axienet_local *lp, off_t reg, dma_addr_t addr) { axienet_dma_out32(lp, reg, lower_32_bits(addr)); + + if (lp->features & XAE_FEATURE_DMA_64BIT) + axienet_dma_out32(lp, reg + 4, upper_32_bits(addr)); } static void desc_set_phys_addr(struct axienet_local *lp, dma_addr_t addr, @@ -1945,6 +1948,29 @@ static int axienet_probe(struct platform_device *pdev) goto free_netdev; } + /* Autodetect the need for 64-bit DMA pointers. + * When the IP is configured for a bus width bigger than 32 bits, + * writing the MSB registers is mandatory, even if they are all 0. + * We can detect this case by writing all 1's to one such register + * and see if that sticks: when the IP is configured for 32 bits + * only, those registers are RES0. + * Those MSB registers were introduced in IP v7.1, which we check first. + */ + if ((axienet_ior(lp, XAE_ID_OFFSET) >> 24) >= 0x9) { + void __iomem *desc = lp->dma_regs + XAXIDMA_TX_CDESC_OFFSET + 4; + + iowrite32(0x0, desc); + if (ioread32(desc) == 0) { /* sanity check */ + iowrite32(0xffffffff, desc); + if (ioread32(desc) > 0) { + lp->features |= XAE_FEATURE_DMA_64BIT; + dev_info(&pdev->dev, + "autodetected 64-bit DMA range\n"); + } + iowrite32(0x0, desc); + } + } + /* Check for Ethernet core IRQ (optional) */ if (lp->eth_irq <= 0) dev_info(&pdev->dev, "Ethernet core IRQ not defined\n"); -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Andre Przywara <andre.przywara@arm.com> To: "David S . Miller" <davem@davemloft.net>, Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Cc: Andrew Lunn <andrew@lunn.ch>, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Michal Simek <michal.simek@xilinx.com>, Robert Hancock <hancock@sedsystems.ca>, rmk+kernel@arm.linux.org.uk, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 13/14] net: axienet: Autodetect 64-bit DMA capability Date: Mon, 9 Mar 2020 18:18:50 +0000 [thread overview] Message-ID: <20200309181851.190164-14-andre.przywara@arm.com> (raw) In-Reply-To: <20200309181851.190164-1-andre.przywara@arm.com> When newer revisions of the Axienet IP are configured for a 64-bit bus, we *need* to write to the MSB part of the an address registers, otherwise the IP won't recognise this as a DMA start condition. This is even true when the actual DMA address comes from the lower 4 GB. To autodetect this configuration, at probe time we write all 1's to such an MSB register, and see if any bits stick. If this is configured for a 32-bit bus, those MSB registers are RES0, so reading back 0 indicates that no MSB writes are necessary. On the other hands reading anything other than 0 indicated the need to write the MSB registers, so we set the respective flag. The actual DMA mask stays at 32-bit for now. To help bisecting, a separate patch will enable allocations from higher addresses. Signed-off-by: Andre Przywara <andre.przywara@arm.com> --- drivers/net/ethernet/xilinx/xilinx_axienet.h | 1 + .../net/ethernet/xilinx/xilinx_axienet_main.c | 26 +++++++++++++++++++ 2 files changed, 27 insertions(+) diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet.h b/drivers/net/ethernet/xilinx/xilinx_axienet.h index 84c4c3655516..fbaf3c987d9c 100644 --- a/drivers/net/ethernet/xilinx/xilinx_axienet.h +++ b/drivers/net/ethernet/xilinx/xilinx_axienet.h @@ -161,6 +161,7 @@ #define XAE_FCC_OFFSET 0x0000040C /* Flow Control Configuration */ #define XAE_EMMC_OFFSET 0x00000410 /* EMAC mode configuration */ #define XAE_PHYC_OFFSET 0x00000414 /* RGMII/SGMII configuration */ +#define XAE_ID_OFFSET 0x000004F8 /* Identification register */ #define XAE_MDIO_MC_OFFSET 0x00000500 /* MII Management Config */ #define XAE_MDIO_MCR_OFFSET 0x00000504 /* MII Management Control */ #define XAE_MDIO_MWD_OFFSET 0x00000508 /* MII Management Write Data */ diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c index edee0666d52c..8c0887b1c009 100644 --- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c +++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c @@ -151,6 +151,9 @@ static void axienet_dma_out_addr(struct axienet_local *lp, off_t reg, dma_addr_t addr) { axienet_dma_out32(lp, reg, lower_32_bits(addr)); + + if (lp->features & XAE_FEATURE_DMA_64BIT) + axienet_dma_out32(lp, reg + 4, upper_32_bits(addr)); } static void desc_set_phys_addr(struct axienet_local *lp, dma_addr_t addr, @@ -1945,6 +1948,29 @@ static int axienet_probe(struct platform_device *pdev) goto free_netdev; } + /* Autodetect the need for 64-bit DMA pointers. + * When the IP is configured for a bus width bigger than 32 bits, + * writing the MSB registers is mandatory, even if they are all 0. + * We can detect this case by writing all 1's to one such register + * and see if that sticks: when the IP is configured for 32 bits + * only, those registers are RES0. + * Those MSB registers were introduced in IP v7.1, which we check first. + */ + if ((axienet_ior(lp, XAE_ID_OFFSET) >> 24) >= 0x9) { + void __iomem *desc = lp->dma_regs + XAXIDMA_TX_CDESC_OFFSET + 4; + + iowrite32(0x0, desc); + if (ioread32(desc) == 0) { /* sanity check */ + iowrite32(0xffffffff, desc); + if (ioread32(desc) > 0) { + lp->features |= XAE_FEATURE_DMA_64BIT; + dev_info(&pdev->dev, + "autodetected 64-bit DMA range\n"); + } + iowrite32(0x0, desc); + } + } + /* Check for Ethernet core IRQ (optional) */ if (lp->eth_irq <= 0) dev_info(&pdev->dev, "Ethernet core IRQ not defined\n"); -- 2.17.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-03-09 18:19 UTC|newest] Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-03-09 18:18 [PATCH v2 00/14] net: axienet: Update error handling and add 64-bit DMA support Andre Przywara 2020-03-09 18:18 ` Andre Przywara 2020-03-09 18:18 ` [PATCH v2 01/14] net: xilinx: temac: Relax Kconfig dependencies Andre Przywara 2020-03-09 18:18 ` Andre Przywara 2020-03-10 11:55 ` Esben Haabendal 2020-03-10 11:55 ` Esben Haabendal 2020-03-09 18:18 ` [PATCH v2 02/14] net: axienet: Convert DMA error handler to a work queue Andre Przywara 2020-03-09 18:18 ` Andre Przywara 2020-03-09 18:18 ` [PATCH v2 03/14] net: axienet: Propagate failure of DMA descriptor setup Andre Przywara 2020-03-09 18:18 ` Andre Przywara 2020-03-09 18:18 ` [PATCH v2 04/14] net: axienet: Fix DMA descriptor cleanup path Andre Przywara 2020-03-09 18:18 ` Andre Przywara 2020-03-09 18:29 ` Andre Przywara 2020-03-09 18:29 ` Andre Przywara 2020-03-09 18:18 ` [PATCH v2 05/14] net: axienet: Improve DMA error handling Andre Przywara 2020-03-09 18:18 ` Andre Przywara 2020-03-09 18:18 ` [PATCH v2 06/14] net: axienet: Factor out TX descriptor chain cleanup Andre Przywara 2020-03-09 18:18 ` Andre Przywara 2020-03-10 0:48 ` David Miller 2020-03-10 0:48 ` David Miller 2020-03-09 18:18 ` [PATCH v2 07/14] net: axienet: Check for DMA mapping errors Andre Przywara 2020-03-09 18:18 ` Andre Przywara 2020-03-09 18:18 ` [PATCH v2 08/14] net: axienet: Mark eth_irq as optional Andre Przywara 2020-03-09 18:18 ` Andre Przywara 2020-03-09 18:18 ` [PATCH v2 09/14] net: axienet: Drop MDIO interrupt registers from ethtools dump Andre Przywara 2020-03-09 18:18 ` Andre Przywara 2020-03-09 18:18 ` [PATCH v2 10/14] net: axienet: Add mii-tool support Andre Przywara 2020-03-09 18:18 ` Andre Przywara 2020-03-09 18:18 ` [PATCH v2 11/14] net: axienet: Wrap DMA pointer writes to prepare for 64 bit Andre Przywara 2020-03-09 18:18 ` Andre Przywara 2020-03-09 18:18 ` [PATCH v2 12/14] net: axienet: Upgrade descriptors to hold 64-bit addresses Andre Przywara 2020-03-09 18:18 ` Andre Przywara 2020-03-09 18:46 ` Robert Hancock 2020-03-09 18:46 ` Robert Hancock 2020-03-10 9:35 ` Andre Przywara 2020-03-10 9:35 ` Andre Przywara 2020-03-10 0:49 ` kbuild test robot 2020-03-09 18:18 ` Andre Przywara [this message] 2020-03-09 18:18 ` [PATCH v2 13/14] net: axienet: Autodetect 64-bit DMA capability Andre Przywara 2020-03-09 18:18 ` [PATCH v2 14/14] net: axienet: Allow DMA to beyond 4GB Andre Przywara 2020-03-09 18:18 ` Andre Przywara
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