From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Pankaj Bharadiya <pankaj.laxminarayan.bharadiya@intel.com>
Cc: jani.nikula@linux.intel.com, daniel@ffwll.ch,
intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org,
airlied@linux.ie, maarten.lankhorst@linux.intel.com,
tzimmermann@suse.de, mripard@kernel.org,
mihail.atanassov@arm.com,
Joonas Lahtinen <joonas.lahtinen@linux.intel.com>,
Rodrigo Vivi <rodrigo.vivi@intel.com>,
linux-kernel@vger.kernel.org, ankit.k.nautiyal@intel.com
Subject: Re: [RFC][PATCH 4/5] drm/i915: Introduce scaling filter related registers and bit fields.
Date: Tue, 10 Mar 2020 18:08:25 +0200 [thread overview]
Message-ID: <20200310160825.GJ13686@intel.com> (raw)
In-Reply-To: <20200225070545.4482-5-pankaj.laxminarayan.bharadiya@intel.com>
On Tue, Feb 25, 2020 at 12:35:44PM +0530, Pankaj Bharadiya wrote:
> Introduce scaler registers and bit fields needed to configure the
> scaling filter in prgrammed mode and configure scaling filter
> coefficients.
>
> Signed-off-by: Pankaj Bharadiya <pankaj.laxminarayan.bharadiya@intel.com>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 34923b1c284c..bba4ad3be611 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7289,6 +7289,18 @@ enum {
> #define _PS_ECC_STAT_2B 0x68AD0
> #define _PS_ECC_STAT_1C 0x691D0
>
> +#define _PS_COEF_SET0_INDEX_1A 0x68198
> +#define _PS_COEF_SET0_INDEX_2A 0x68298
> +#define _PS_COEF_SET0_INDEX_1B 0x68998
> +#define _PS_COEF_SET0_INDEX_2B 0x68A98
> +
> +#define _PS_COEF_SET0_DATA_1A 0x6819C
> +#define _PS_COEF_SET0_DATA_2A 0x6829C
> +#define _PS_COEF_SET0_DATA_1B 0x6899C
> +#define _PS_COEF_SET0_DATA_2B 0x68A9C
> +
Sourious whitespace.
> +#define _PS_COEE_INDEX_AUTO_INC (1 << 10)
Wrong indentation (though looks like most scaler register
definitions get that wrong already), and the leading '_' shouldn't
be here at all.
> +
> #define _ID(id, a, b) _PICK_EVEN(id, a, b)
> #define SKL_PS_CTRL(pipe, id) _MMIO_PIPE(pipe, \
> _ID(id, _PS_1A_CTRL, _PS_2A_CTRL), \
> @@ -7318,6 +7330,14 @@ enum {
> _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \
> _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B))
>
> +#define SKL_PS_COEF_INDEX_SET0(pipe, id) _MMIO_PIPE(pipe, \
> + _ID(id, _PS_COEF_SET0_INDEX_1A, _PS_COEF_SET0_INDEX_2A), \
> + _ID(id, _PS_COEF_SET0_INDEX_1B, _PS_COEF_SET0_INDEX_2B))
> +
> +#define SKL_PS_COEF_DATA_SET0(pipe, id) _MMIO_PIPE(pipe, \
> + _ID(id, _PS_COEF_SET0_DATA_1A, _PS_COEF_SET0_DATA_2A), \
> + _ID(id, _PS_COEF_SET0_DATA_1B, _PS_COEF_SET0_DATA_2B))
Please parametrize by 'set' as well.
> +
> /* legacy palette */
> #define _LGC_PALETTE_A 0x4a000
> #define _LGC_PALETTE_B 0x4a800
> --
> 2.23.0
--
Ville Syrjälä
Intel
WARNING: multiple messages have this Message-ID (diff)
From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Pankaj Bharadiya <pankaj.laxminarayan.bharadiya@intel.com>
Cc: tzimmermann@suse.de, airlied@linux.ie,
intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org,
dri-devel@lists.freedesktop.org,
Rodrigo Vivi <rodrigo.vivi@intel.com>,
ankit.k.nautiyal@intel.com, mihail.atanassov@arm.com
Subject: Re: [RFC][PATCH 4/5] drm/i915: Introduce scaling filter related registers and bit fields.
Date: Tue, 10 Mar 2020 18:08:25 +0200 [thread overview]
Message-ID: <20200310160825.GJ13686@intel.com> (raw)
In-Reply-To: <20200225070545.4482-5-pankaj.laxminarayan.bharadiya@intel.com>
On Tue, Feb 25, 2020 at 12:35:44PM +0530, Pankaj Bharadiya wrote:
> Introduce scaler registers and bit fields needed to configure the
> scaling filter in prgrammed mode and configure scaling filter
> coefficients.
>
> Signed-off-by: Pankaj Bharadiya <pankaj.laxminarayan.bharadiya@intel.com>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 34923b1c284c..bba4ad3be611 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7289,6 +7289,18 @@ enum {
> #define _PS_ECC_STAT_2B 0x68AD0
> #define _PS_ECC_STAT_1C 0x691D0
>
> +#define _PS_COEF_SET0_INDEX_1A 0x68198
> +#define _PS_COEF_SET0_INDEX_2A 0x68298
> +#define _PS_COEF_SET0_INDEX_1B 0x68998
> +#define _PS_COEF_SET0_INDEX_2B 0x68A98
> +
> +#define _PS_COEF_SET0_DATA_1A 0x6819C
> +#define _PS_COEF_SET0_DATA_2A 0x6829C
> +#define _PS_COEF_SET0_DATA_1B 0x6899C
> +#define _PS_COEF_SET0_DATA_2B 0x68A9C
> +
Sourious whitespace.
> +#define _PS_COEE_INDEX_AUTO_INC (1 << 10)
Wrong indentation (though looks like most scaler register
definitions get that wrong already), and the leading '_' shouldn't
be here at all.
> +
> #define _ID(id, a, b) _PICK_EVEN(id, a, b)
> #define SKL_PS_CTRL(pipe, id) _MMIO_PIPE(pipe, \
> _ID(id, _PS_1A_CTRL, _PS_2A_CTRL), \
> @@ -7318,6 +7330,14 @@ enum {
> _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \
> _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B))
>
> +#define SKL_PS_COEF_INDEX_SET0(pipe, id) _MMIO_PIPE(pipe, \
> + _ID(id, _PS_COEF_SET0_INDEX_1A, _PS_COEF_SET0_INDEX_2A), \
> + _ID(id, _PS_COEF_SET0_INDEX_1B, _PS_COEF_SET0_INDEX_2B))
> +
> +#define SKL_PS_COEF_DATA_SET0(pipe, id) _MMIO_PIPE(pipe, \
> + _ID(id, _PS_COEF_SET0_DATA_1A, _PS_COEF_SET0_DATA_2A), \
> + _ID(id, _PS_COEF_SET0_DATA_1B, _PS_COEF_SET0_DATA_2B))
Please parametrize by 'set' as well.
> +
> /* legacy palette */
> #define _LGC_PALETTE_A 0x4a000
> #define _LGC_PALETTE_B 0x4a800
> --
> 2.23.0
--
Ville Syrjälä
Intel
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
WARNING: multiple messages have this Message-ID (diff)
From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Pankaj Bharadiya <pankaj.laxminarayan.bharadiya@intel.com>
Cc: mripard@kernel.org, tzimmermann@suse.de, airlied@linux.ie,
intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org,
dri-devel@lists.freedesktop.org, ankit.k.nautiyal@intel.com,
mihail.atanassov@arm.com
Subject: Re: [Intel-gfx] [RFC][PATCH 4/5] drm/i915: Introduce scaling filter related registers and bit fields.
Date: Tue, 10 Mar 2020 18:08:25 +0200 [thread overview]
Message-ID: <20200310160825.GJ13686@intel.com> (raw)
In-Reply-To: <20200225070545.4482-5-pankaj.laxminarayan.bharadiya@intel.com>
On Tue, Feb 25, 2020 at 12:35:44PM +0530, Pankaj Bharadiya wrote:
> Introduce scaler registers and bit fields needed to configure the
> scaling filter in prgrammed mode and configure scaling filter
> coefficients.
>
> Signed-off-by: Pankaj Bharadiya <pankaj.laxminarayan.bharadiya@intel.com>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 34923b1c284c..bba4ad3be611 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7289,6 +7289,18 @@ enum {
> #define _PS_ECC_STAT_2B 0x68AD0
> #define _PS_ECC_STAT_1C 0x691D0
>
> +#define _PS_COEF_SET0_INDEX_1A 0x68198
> +#define _PS_COEF_SET0_INDEX_2A 0x68298
> +#define _PS_COEF_SET0_INDEX_1B 0x68998
> +#define _PS_COEF_SET0_INDEX_2B 0x68A98
> +
> +#define _PS_COEF_SET0_DATA_1A 0x6819C
> +#define _PS_COEF_SET0_DATA_2A 0x6829C
> +#define _PS_COEF_SET0_DATA_1B 0x6899C
> +#define _PS_COEF_SET0_DATA_2B 0x68A9C
> +
Sourious whitespace.
> +#define _PS_COEE_INDEX_AUTO_INC (1 << 10)
Wrong indentation (though looks like most scaler register
definitions get that wrong already), and the leading '_' shouldn't
be here at all.
> +
> #define _ID(id, a, b) _PICK_EVEN(id, a, b)
> #define SKL_PS_CTRL(pipe, id) _MMIO_PIPE(pipe, \
> _ID(id, _PS_1A_CTRL, _PS_2A_CTRL), \
> @@ -7318,6 +7330,14 @@ enum {
> _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \
> _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B))
>
> +#define SKL_PS_COEF_INDEX_SET0(pipe, id) _MMIO_PIPE(pipe, \
> + _ID(id, _PS_COEF_SET0_INDEX_1A, _PS_COEF_SET0_INDEX_2A), \
> + _ID(id, _PS_COEF_SET0_INDEX_1B, _PS_COEF_SET0_INDEX_2B))
> +
> +#define SKL_PS_COEF_DATA_SET0(pipe, id) _MMIO_PIPE(pipe, \
> + _ID(id, _PS_COEF_SET0_DATA_1A, _PS_COEF_SET0_DATA_2A), \
> + _ID(id, _PS_COEF_SET0_DATA_1B, _PS_COEF_SET0_DATA_2B))
Please parametrize by 'set' as well.
> +
> /* legacy palette */
> #define _LGC_PALETTE_A 0x4a000
> #define _LGC_PALETTE_B 0x4a800
> --
> 2.23.0
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2020-03-10 16:08 UTC|newest]
Thread overview: 83+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-25 7:05 [RFC][PATCH 0/5] Introduce drm scaling filter property Pankaj Bharadiya
2020-02-25 7:05 ` [Intel-gfx] " Pankaj Bharadiya
2020-02-25 7:05 ` Pankaj Bharadiya
2020-02-25 7:05 ` [RFC][PATCH 1/5] drm: Introduce " Pankaj Bharadiya
2020-02-25 7:05 ` [Intel-gfx] " Pankaj Bharadiya
2020-02-25 7:05 ` Pankaj Bharadiya
2020-02-25 9:56 ` Jani Nikula
2020-02-25 9:56 ` [Intel-gfx] " Jani Nikula
2020-02-25 9:56 ` Jani Nikula
2020-02-25 10:09 ` Laxminarayan Bharadiya, Pankaj
2020-02-25 10:09 ` [Intel-gfx] " Laxminarayan Bharadiya, Pankaj
2020-02-25 10:09 ` Laxminarayan Bharadiya, Pankaj
2020-02-25 11:07 ` Jani Nikula
2020-02-25 11:07 ` [Intel-gfx] " Jani Nikula
2020-02-25 11:07 ` Jani Nikula
2020-03-10 16:01 ` Ville Syrjälä
2020-03-10 16:01 ` [Intel-gfx] " Ville Syrjälä
2020-03-10 16:01 ` Ville Syrjälä
2020-03-16 8:31 ` Daniel Vetter
2020-03-16 8:31 ` [Intel-gfx] " Daniel Vetter
2020-03-16 8:31 ` Daniel Vetter
2020-03-16 15:14 ` Ville Syrjälä
2020-03-16 15:14 ` [Intel-gfx] " Ville Syrjälä
2020-03-16 15:14 ` Ville Syrjälä
2020-02-25 7:05 ` [RFC][PATCH 2/5] drm/drm-kms.rst: Add Scaling filter property documentation Pankaj Bharadiya
2020-02-25 7:05 ` [Intel-gfx] " Pankaj Bharadiya
2020-02-25 7:05 ` Pankaj Bharadiya
2020-02-25 7:05 ` [RFC][PATCH 3/5] drm/i915: Enable scaling filter for plane and pipe Pankaj Bharadiya
2020-02-25 7:05 ` [Intel-gfx] " Pankaj Bharadiya
2020-02-25 7:05 ` Pankaj Bharadiya
2020-03-10 16:05 ` Ville Syrjälä
2020-03-10 16:05 ` [Intel-gfx] " Ville Syrjälä
2020-03-10 16:05 ` Ville Syrjälä
2020-03-12 8:58 ` Laxminarayan Bharadiya, Pankaj
2020-03-12 8:58 ` [Intel-gfx] " Laxminarayan Bharadiya, Pankaj
2020-03-12 8:58 ` Laxminarayan Bharadiya, Pankaj
2020-03-12 12:27 ` Ville Syrjälä
2020-03-12 12:27 ` [Intel-gfx] " Ville Syrjälä
2020-03-12 12:27 ` Ville Syrjälä
2020-02-25 7:05 ` [RFC][PATCH 4/5] drm/i915: Introduce scaling filter related registers and bit fields Pankaj Bharadiya
2020-02-25 7:05 ` [Intel-gfx] " Pankaj Bharadiya
2020-02-25 7:05 ` Pankaj Bharadiya
2020-03-10 16:08 ` Ville Syrjälä [this message]
2020-03-10 16:08 ` [Intel-gfx] " Ville Syrjälä
2020-03-10 16:08 ` Ville Syrjälä
2020-02-25 7:05 ` [RFC][PATCH 5/5] drm/i915/display: Add Nearest-neighbor based integer scaling support Pankaj Bharadiya
2020-02-25 7:05 ` [Intel-gfx] " Pankaj Bharadiya
2020-02-25 7:05 ` Pankaj Bharadiya
2020-02-25 7:29 ` [Intel-gfx] " Daniel Stone
2020-02-25 7:29 ` Daniel Stone
2020-02-25 7:29 ` Daniel Stone
2020-02-28 5:50 ` Laxminarayan Bharadiya, Pankaj
2020-02-28 5:50 ` Laxminarayan Bharadiya, Pankaj
2020-02-28 5:50 ` Laxminarayan Bharadiya, Pankaj
2020-03-10 16:17 ` Ville Syrjälä
2020-03-10 16:17 ` [Intel-gfx] " Ville Syrjälä
2020-03-10 16:17 ` Ville Syrjälä
2020-03-12 9:13 ` Laxminarayan Bharadiya, Pankaj
2020-03-12 9:13 ` [Intel-gfx] " Laxminarayan Bharadiya, Pankaj
2020-03-12 9:13 ` Laxminarayan Bharadiya, Pankaj
2020-03-12 13:54 ` Ville Syrjälä
2020-03-12 13:54 ` [Intel-gfx] " Ville Syrjälä
2020-03-12 13:54 ` Ville Syrjälä
2020-03-13 8:45 ` Laxminarayan Bharadiya, Pankaj
2020-03-13 8:45 ` [Intel-gfx] " Laxminarayan Bharadiya, Pankaj
2020-03-13 8:45 ` Laxminarayan Bharadiya, Pankaj
2020-03-13 19:53 ` Ville Syrjälä
2020-03-13 19:53 ` [Intel-gfx] " Ville Syrjälä
2020-03-13 19:53 ` Ville Syrjälä
2020-02-25 7:24 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce drm scaling filter property Patchwork
2020-02-25 7:50 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2020-03-12 14:04 ` [RFC][PATCH 0/5] " Ville Syrjälä
2020-03-12 14:04 ` [Intel-gfx] " Ville Syrjälä
2020-03-12 14:04 ` Ville Syrjälä
2020-03-12 15:37 ` Laxminarayan Bharadiya, Pankaj
2020-03-12 15:37 ` [Intel-gfx] " Laxminarayan Bharadiya, Pankaj
2020-03-12 15:37 ` Laxminarayan Bharadiya, Pankaj
2020-03-12 16:01 ` Ville Syrjälä
2020-03-12 16:01 ` [Intel-gfx] " Ville Syrjälä
2020-03-12 16:01 ` Ville Syrjälä
2020-03-13 10:35 ` Pekka Paalanen
2020-03-13 10:35 ` [Intel-gfx] " Pekka Paalanen
2020-03-13 10:35 ` Pekka Paalanen
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