From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v3 5/5] drm/i915: Remove unneeded hack now for CDCLK
Date: Mon, 30 Mar 2020 15:23:54 +0300 [thread overview]
Message-ID: <20200330122354.24752-6-stanislav.lisovskiy@intel.com> (raw)
In-Reply-To: <20200330122354.24752-1-stanislav.lisovskiy@intel.com>
No need to bump up CDCLK now, as it is now correctly
calculated, accounting for DBuf BW as BSpec says.
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 12 ------------
1 file changed, 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 036774e7f3ec..13e7ea6f471e 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2077,18 +2077,6 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
/* Account for additional needs from the planes */
min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk);
- /*
- * HACK. Currently for TGL platforms we calculate
- * min_cdclk initially based on pixel_rate divided
- * by 2, accounting for also plane requirements,
- * however in some cases the lowest possible CDCLK
- * doesn't work and causing the underruns.
- * Explicitly stating here that this seems to be currently
- * rather a Hack, than final solution.
- */
- if (IS_TIGERLAKE(dev_priv))
- min_cdclk = max(min_cdclk, (int)crtc_state->pixel_rate);
-
/*
* Similar story as with skl_write_plane_wm and intel_enable_sagv
* - in some certain driver parts, we don't have any guarantee that
--
2.24.1.485.gad05a3d8e5
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next prev parent reply other threads:[~2020-03-30 12:27 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-30 12:23 [Intel-gfx] [PATCH v3 0/5] Consider DBuf bandwidth when calculating CDCLK Stanislav Lisovskiy
2020-03-30 12:23 ` [Intel-gfx] [PATCH v3 1/5] drm/i915: Decouple cdclk calculation from modeset checks Stanislav Lisovskiy
2020-03-30 15:44 ` Ville Syrjälä
2020-04-07 7:33 ` [Intel-gfx] [PATCH v4 " Stanislav Lisovskiy
2020-04-07 16:15 ` Ville Syrjälä
2020-03-30 12:23 ` [Intel-gfx] [PATCH v3 2/5] drm/i915: Force recalculate min_cdclk if planes config changed Stanislav Lisovskiy
2020-03-30 16:18 ` Ville Syrjälä
2020-03-30 17:56 ` Lisovskiy, Stanislav
2020-04-07 7:36 ` [Intel-gfx] [PATCH v4 " Stanislav Lisovskiy
2020-03-30 12:23 ` [Intel-gfx] [PATCH v3 3/5] drm/i915: Introduce for_each_dbuf_slice_in_mask macro Stanislav Lisovskiy
2020-03-30 16:07 ` Ville Syrjälä
2020-04-07 7:38 ` [Intel-gfx] [PATCH v4 " Stanislav Lisovskiy
2020-03-30 12:23 ` [Intel-gfx] [PATCH v3 4/5] drm/i915: Adjust CDCLK accordingly to our DBuf bw needs Stanislav Lisovskiy
2020-03-30 17:07 ` Ville Syrjälä
2020-03-30 18:16 ` Lisovskiy, Stanislav
2020-04-07 16:26 ` Ville Syrjälä
2020-04-07 7:39 ` [Intel-gfx] [PATCH v4 " Stanislav Lisovskiy
2020-03-30 12:23 ` Stanislav Lisovskiy [this message]
2020-03-30 18:07 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Consider DBuf bandwidth when calculating CDCLK (rev3) Patchwork
2020-04-07 8:03 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Consider DBuf bandwidth when calculating CDCLK (rev7) Patchwork
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