From: Zhenyu Ye <yezhenyu2@huawei.com>
To: <peterz@infradead.org>, <mark.rutland@arm.com>, <will@kernel.org>,
<catalin.marinas@arm.com>, <aneesh.kumar@linux.ibm.com>,
<akpm@linux-foundation.org>, <npiggin@gmail.com>, <arnd@arndb.de>,
<rostedt@goodmis.org>, <maz@kernel.org>, <suzuki.poulose@arm.com>,
<tglx@linutronix.de>, <yuzhao@google.com>, <Dave.Martin@arm.com>,
<steven.price@arm.com>, <broonie@kernel.org>,
<guohanjun@huawei.com>, <corbet@lwn.net>, <vgupta@synopsys.com>,
<tony.luck@intel.com>
Cc: <yezhenyu2@huawei.com>, <linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <linux-arch@vger.kernel.org>,
<linux-mm@kvack.org>, <arm@kernel.org>, <xiexiangyou@huawei.com>,
<prime.zeng@hisilicon.com>, <zhangshaokun@hisilicon.com>,
<kuhn.chenqun@huawei.com>
Subject: [RFC PATCH v5 2/8] arm64: Add level-hinted TLB invalidation helper
Date: Tue, 31 Mar 2020 22:29:21 +0800 [thread overview]
Message-ID: <20200331142927.1237-3-yezhenyu2@huawei.com> (raw)
In-Reply-To: <20200331142927.1237-1-yezhenyu2@huawei.com>
From: Marc Zyngier <maz@kernel.org>
Add a level-hinted TLB invalidation helper that only gets used if
ARMv8.4-TTL gets detected.
Signed-off-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Zhenyu Ye <yezhenyu2@huawei.com>
---
arch/arm64/include/asm/tlbflush.h | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h
index bc3949064725..5f9f189bc6d2 100644
--- a/arch/arm64/include/asm/tlbflush.h
+++ b/arch/arm64/include/asm/tlbflush.h
@@ -10,6 +10,7 @@
#ifndef __ASSEMBLY__
+#include <linux/bitfield.h>
#include <linux/mm_types.h>
#include <linux/sched.h>
#include <asm/cputype.h>
@@ -59,6 +60,35 @@
__ta; \
})
+#define TLBI_TTL_MASK GENMASK_ULL(47, 44)
+
+#define __tlbi_level(op, addr, level) \
+ do { \
+ u64 arg = addr; \
+ \
+ if (cpus_have_const_cap(ARM64_HAS_ARMv8_4_TTL) && \
+ level) { \
+ u64 ttl = level; \
+ \
+ switch (PAGE_SIZE) { \
+ case SZ_4K: \
+ ttl |= 1 << 2; \
+ break; \
+ case SZ_16K: \
+ ttl |= 2 << 2; \
+ break; \
+ case SZ_64K: \
+ ttl |= 3 << 2; \
+ break; \
+ } \
+ \
+ arg &= ~TLBI_TTL_MASK; \
+ arg |= FIELD_PREP(TLBI_TTL_MASK, ttl); \
+ } \
+ \
+ __tlbi(op, arg); \
+ } while (0)
+
/*
* TLB Invalidation
* ================
--
2.19.1
WARNING: multiple messages have this Message-ID (diff)
From: Zhenyu Ye <yezhenyu2@huawei.com>
To: peterz@infradead.org, mark.rutland@arm.com, will@kernel.org,
catalin.marinas@arm.com, aneesh.kumar@linux.ibm.com,
akpm@linux-foundation.org, npiggin@gmail.com, arnd@arndb.de,
rostedt@goodmis.org, maz@kernel.org, suzuki.poulose@arm.com,
tglx@linutronix.de, yuzhao@google.com, Dave.Martin@arm.com,
steven.price@arm.com, broonie@kernel.org, guohanjun@huawei.com,
corbet@lwn.net, vgupta@synopsys.com, tony.luck@intel.com
Cc: yezhenyu2@huawei.com, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org,
linux-mm@kvack.org, arm@kernel.org, xiexiangyou@huawei.com,
prime.zeng@hisilicon.com, zhangshaokun@hisilicon.com,
kuhn.chenqun@huawei.com
Subject: [RFC PATCH v5 2/8] arm64: Add level-hinted TLB invalidation helper
Date: Tue, 31 Mar 2020 22:29:21 +0800 [thread overview]
Message-ID: <20200331142927.1237-3-yezhenyu2@huawei.com> (raw)
In-Reply-To: <20200331142927.1237-1-yezhenyu2@huawei.com>
From: Marc Zyngier <maz@kernel.org>
Add a level-hinted TLB invalidation helper that only gets used if
ARMv8.4-TTL gets detected.
Signed-off-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Zhenyu Ye <yezhenyu2@huawei.com>
---
arch/arm64/include/asm/tlbflush.h | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h
index bc3949064725..5f9f189bc6d2 100644
--- a/arch/arm64/include/asm/tlbflush.h
+++ b/arch/arm64/include/asm/tlbflush.h
@@ -10,6 +10,7 @@
#ifndef __ASSEMBLY__
+#include <linux/bitfield.h>
#include <linux/mm_types.h>
#include <linux/sched.h>
#include <asm/cputype.h>
@@ -59,6 +60,35 @@
__ta; \
})
+#define TLBI_TTL_MASK GENMASK_ULL(47, 44)
+
+#define __tlbi_level(op, addr, level) \
+ do { \
+ u64 arg = addr; \
+ \
+ if (cpus_have_const_cap(ARM64_HAS_ARMv8_4_TTL) && \
+ level) { \
+ u64 ttl = level; \
+ \
+ switch (PAGE_SIZE) { \
+ case SZ_4K: \
+ ttl |= 1 << 2; \
+ break; \
+ case SZ_16K: \
+ ttl |= 2 << 2; \
+ break; \
+ case SZ_64K: \
+ ttl |= 3 << 2; \
+ break; \
+ } \
+ \
+ arg &= ~TLBI_TTL_MASK; \
+ arg |= FIELD_PREP(TLBI_TTL_MASK, ttl); \
+ } \
+ \
+ __tlbi(op, arg); \
+ } while (0)
+
/*
* TLB Invalidation
* ================
--
2.19.1
WARNING: multiple messages have this Message-ID (diff)
From: Zhenyu Ye <yezhenyu2@huawei.com>
To: <peterz@infradead.org>, <mark.rutland@arm.com>, <will@kernel.org>,
<catalin.marinas@arm.com>, <aneesh.kumar@linux.ibm.com>,
<akpm@linux-foundation.org>, <npiggin@gmail.com>, <arnd@arndb.de>,
<rostedt@goodmis.org>, <maz@kernel.org>, <suzuki.poulose@arm.com>,
<tglx@linutronix.de>, <yuzhao@google.com>, <Dave.Martin@arm.com>,
<steven.price@arm.com>, <broonie@kernel.org>,
<guohanjun@huawei.com>, <corbet@lwn.net>, <vgupta@synopsys.com>,
<tony.luck@intel.com>
Cc: linux-arch@vger.kernel.org, yezhenyu2@huawei.com,
linux-kernel@vger.kernel.org, xiexiangyou@huawei.com,
zhangshaokun@hisilicon.com, linux-mm@kvack.org, arm@kernel.org,
prime.zeng@hisilicon.com, kuhn.chenqun@huawei.com,
linux-arm-kernel@lists.infradead.org
Subject: [RFC PATCH v5 2/8] arm64: Add level-hinted TLB invalidation helper
Date: Tue, 31 Mar 2020 22:29:21 +0800 [thread overview]
Message-ID: <20200331142927.1237-3-yezhenyu2@huawei.com> (raw)
In-Reply-To: <20200331142927.1237-1-yezhenyu2@huawei.com>
From: Marc Zyngier <maz@kernel.org>
Add a level-hinted TLB invalidation helper that only gets used if
ARMv8.4-TTL gets detected.
Signed-off-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Zhenyu Ye <yezhenyu2@huawei.com>
---
arch/arm64/include/asm/tlbflush.h | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h
index bc3949064725..5f9f189bc6d2 100644
--- a/arch/arm64/include/asm/tlbflush.h
+++ b/arch/arm64/include/asm/tlbflush.h
@@ -10,6 +10,7 @@
#ifndef __ASSEMBLY__
+#include <linux/bitfield.h>
#include <linux/mm_types.h>
#include <linux/sched.h>
#include <asm/cputype.h>
@@ -59,6 +60,35 @@
__ta; \
})
+#define TLBI_TTL_MASK GENMASK_ULL(47, 44)
+
+#define __tlbi_level(op, addr, level) \
+ do { \
+ u64 arg = addr; \
+ \
+ if (cpus_have_const_cap(ARM64_HAS_ARMv8_4_TTL) && \
+ level) { \
+ u64 ttl = level; \
+ \
+ switch (PAGE_SIZE) { \
+ case SZ_4K: \
+ ttl |= 1 << 2; \
+ break; \
+ case SZ_16K: \
+ ttl |= 2 << 2; \
+ break; \
+ case SZ_64K: \
+ ttl |= 3 << 2; \
+ break; \
+ } \
+ \
+ arg &= ~TLBI_TTL_MASK; \
+ arg |= FIELD_PREP(TLBI_TTL_MASK, ttl); \
+ } \
+ \
+ __tlbi(op, arg); \
+ } while (0)
+
/*
* TLB Invalidation
* ================
--
2.19.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-03-31 14:30 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-31 14:29 [RFC PATCH v5 0/8] arm64: tlb: add support for TTL feature Zhenyu Ye
2020-03-31 14:29 ` Zhenyu Ye
2020-03-31 14:29 ` Zhenyu Ye
2020-03-31 14:29 ` [RFC PATCH v5 1/8] arm64: Detect the ARMv8.4 " Zhenyu Ye
2020-03-31 14:29 ` Zhenyu Ye
2020-03-31 14:29 ` Zhenyu Ye
2020-03-31 14:29 ` Zhenyu Ye [this message]
2020-03-31 14:29 ` [RFC PATCH v5 2/8] arm64: Add level-hinted TLB invalidation helper Zhenyu Ye
2020-03-31 14:29 ` Zhenyu Ye
2020-03-31 14:29 ` [RFC PATCH v5 3/8] arm64: Add tlbi_user_level " Zhenyu Ye
2020-03-31 14:29 ` Zhenyu Ye
2020-03-31 14:29 ` Zhenyu Ye
2020-03-31 14:29 ` [RFC PATCH v5 4/8] mm: tlb: Pass struct mmu_gather to flush_pmd_tlb_range Zhenyu Ye
2020-03-31 14:29 ` Zhenyu Ye
2020-03-31 14:29 ` Zhenyu Ye
2020-03-31 15:13 ` Peter Zijlstra
2020-03-31 15:13 ` Peter Zijlstra
2020-04-01 8:51 ` Zhenyu Ye
2020-04-01 8:51 ` Zhenyu Ye
2020-04-01 8:51 ` Zhenyu Ye
2020-04-01 8:51 ` Zhenyu Ye
2020-04-01 12:20 ` Peter Zijlstra
2020-04-01 12:20 ` Peter Zijlstra
2020-04-01 12:20 ` Peter Zijlstra
2020-04-02 11:24 ` Zhenyu Ye
2020-04-02 11:24 ` Zhenyu Ye
2020-04-02 11:24 ` Zhenyu Ye
2020-04-02 16:38 ` Peter Zijlstra
2020-04-02 16:38 ` Peter Zijlstra
2020-04-02 16:38 ` Peter Zijlstra
2020-04-03 5:14 ` Zhenyu Ye
2020-04-03 5:14 ` Zhenyu Ye
2020-04-03 5:14 ` Zhenyu Ye
2020-04-03 5:14 ` Zhenyu Ye
2020-04-08 9:00 ` Zhenyu Ye
2020-04-08 9:00 ` Zhenyu Ye
2020-04-08 9:00 ` Zhenyu Ye
2020-03-31 14:29 ` [RFC PATCH v5 5/8] mm: tlb: Pass struct mmu_gather to flush_pud_tlb_range Zhenyu Ye
2020-03-31 14:29 ` Zhenyu Ye
2020-03-31 14:29 ` Zhenyu Ye
2020-03-31 14:29 ` [RFC PATCH v5 6/8] mm: tlb: Pass struct mmu_gather to flush_hugetlb_tlb_range Zhenyu Ye
2020-03-31 14:29 ` Zhenyu Ye
2020-03-31 14:29 ` Zhenyu Ye
2020-03-31 14:29 ` [RFC PATCH v5 7/8] mm: tlb: Pass struct mmu_gather to flush_tlb_range Zhenyu Ye
2020-03-31 14:29 ` Zhenyu Ye
2020-03-31 14:29 ` Zhenyu Ye
2020-03-31 21:08 ` kbuild test robot
2020-03-31 14:29 ` [RFC PATCH v5 8/8] arm64: tlb: Set the TTL field in flush_tlb_range Zhenyu Ye
2020-03-31 14:29 ` Zhenyu Ye
2020-03-31 14:29 ` Zhenyu Ye
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