From: "Clément Péron" <peron.clem@gmail.com>
To: Maxime Ripard <mripard@kernel.org>, Chen-Yu Tsai <wens@csie.org>,
Rob Herring <robh+dt@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-sunxi <linux-sunxi@googlegroups.com>,
"Ondrej Jirman" <megous@megous.com>,
"Clément Péron" <peron.clem@gmail.com>
Subject: [PATCH v3 1/7] arm64: dts: allwinner: h6: Add CPU Operating Performance Points table
Date: Sun, 19 Apr 2020 15:50:05 +0200 [thread overview]
Message-ID: <20200419135011.18010-2-peron.clem@gmail.com> (raw)
In-Reply-To: <20200419135011.18010-1-peron.clem@gmail.com>
From: Ondrej Jirman <megous@megous.com>
Add an Operating Performance Points table for the CPU cores to
enable Dynamic Voltage & Frequency Scaling on the H6.
Signed-off-by: Ondrej Jirman <megous@megous.com>
Signed-off-by: Clément Péron <peron.clem@gmail.com>
---
.../boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi | 121 ++++++++++++++++++
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 4 +
2 files changed, 125 insertions(+)
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi
new file mode 100644
index 000000000000..9ebd97b04b1a
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi
@@ -0,0 +1,121 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (C) 2020 Ondrej Jirman <megous@megous.com>
+// Copyright (C) 2020 Clément Péron <peron.clem@gmail.com>
+
+/ {
+ cpu_opp_table: cpu-opp-table {
+ compatible = "allwinner,sun50i-h6-operating-points";
+ nvmem-cells = <&cpu_speed_grade>;
+ opp-shared;
+
+ opp@480000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <480000000>;
+
+ opp-microvolt-speed0 = <880000>;
+ opp-microvolt-speed1 = <820000>;
+ opp-microvolt-speed2 = <820000>;
+ };
+
+ opp@720000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <720000000>;
+
+ opp-microvolt-speed0 = <880000>;
+ opp-microvolt-speed1 = <820000>;
+ opp-microvolt-speed2 = <820000>;
+ };
+
+ opp@816000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <816000000>;
+
+ opp-microvolt-speed0 = <880000>;
+ opp-microvolt-speed1 = <820000>;
+ opp-microvolt-speed2 = <820000>;
+ };
+
+ opp@888000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <888000000>;
+
+ opp-microvolt-speed0 = <880000>;
+ opp-microvolt-speed1 = <820000>;
+ opp-microvolt-speed2 = <820000>;
+ };
+
+ opp@1080000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <1080000000>;
+
+ opp-microvolt-speed0 = <940000>;
+ opp-microvolt-speed1 = <880000>;
+ opp-microvolt-speed2 = <880000>;
+ };
+
+ opp@1320000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <1320000000>;
+
+ opp-microvolt-speed0 = <1000000>;
+ opp-microvolt-speed1 = <940000>;
+ opp-microvolt-speed2 = <940000>;
+ };
+
+ opp@1488000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <1488000000>;
+
+ opp-microvolt-speed0 = <1060000>;
+ opp-microvolt-speed1 = <1000000>;
+ opp-microvolt-speed2 = <1000000>;
+ };
+
+ opp@1608000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <1608000000>;
+
+ opp-microvolt-speed0 = <1090000>;
+ opp-microvolt-speed1 = <1030000>;
+ opp-microvolt-speed2 = <1030000>;
+ };
+
+ opp@1704000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <1704000000>;
+
+ opp-microvolt-speed0 = <1120000>;
+ opp-microvolt-speed1 = <1060000>;
+ opp-microvolt-speed2 = <1060000>;
+ };
+
+ opp@1800000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <1800000000>;
+
+ opp-microvolt-speed0 = <1160000>;
+ opp-microvolt-speed1 = <1100000>;
+ opp-microvolt-speed2 = <1100000>;
+ };
+ };
+};
+
+&cpu0 {
+ operating-points-v2 = <&cpu_opp_table>;
+ #cooling-cells = <2>;
+};
+
+&cpu1 {
+ operating-points-v2 = <&cpu_opp_table>;
+ #cooling-cells = <2>;
+};
+
+&cpu2 {
+ operating-points-v2 = <&cpu_opp_table>;
+ #cooling-cells = <2>;
+};
+
+&cpu3 {
+ operating-points-v2 = <&cpu_opp_table>;
+ #cooling-cells = <2>;
+};
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index 60da1627772b..83e32f9c4977 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -258,6 +258,10 @@
ths_calibration: thermal-sensor-calibration@14 {
reg = <0x14 0x8>;
};
+
+ cpu_speed_grade: cpu-speed-grade@1c {
+ reg = <0x1c 0x4>;
+ };
};
watchdog: watchdog@30090a0 {
--
2.20.1
WARNING: multiple messages have this Message-ID (diff)
From: "Clément Péron" <peron.clem@gmail.com>
To: Maxime Ripard <mripard@kernel.org>, Chen-Yu Tsai <wens@csie.org>,
Rob Herring <robh+dt@kernel.org>
Cc: "Ondrej Jirman" <megous@megous.com>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-sunxi <linux-sunxi@googlegroups.com>,
"Clément Péron" <peron.clem@gmail.com>,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 1/7] arm64: dts: allwinner: h6: Add CPU Operating Performance Points table
Date: Sun, 19 Apr 2020 15:50:05 +0200 [thread overview]
Message-ID: <20200419135011.18010-2-peron.clem@gmail.com> (raw)
In-Reply-To: <20200419135011.18010-1-peron.clem@gmail.com>
From: Ondrej Jirman <megous@megous.com>
Add an Operating Performance Points table for the CPU cores to
enable Dynamic Voltage & Frequency Scaling on the H6.
Signed-off-by: Ondrej Jirman <megous@megous.com>
Signed-off-by: Clément Péron <peron.clem@gmail.com>
---
.../boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi | 121 ++++++++++++++++++
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 4 +
2 files changed, 125 insertions(+)
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi
new file mode 100644
index 000000000000..9ebd97b04b1a
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi
@@ -0,0 +1,121 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (C) 2020 Ondrej Jirman <megous@megous.com>
+// Copyright (C) 2020 Clément Péron <peron.clem@gmail.com>
+
+/ {
+ cpu_opp_table: cpu-opp-table {
+ compatible = "allwinner,sun50i-h6-operating-points";
+ nvmem-cells = <&cpu_speed_grade>;
+ opp-shared;
+
+ opp@480000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <480000000>;
+
+ opp-microvolt-speed0 = <880000>;
+ opp-microvolt-speed1 = <820000>;
+ opp-microvolt-speed2 = <820000>;
+ };
+
+ opp@720000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <720000000>;
+
+ opp-microvolt-speed0 = <880000>;
+ opp-microvolt-speed1 = <820000>;
+ opp-microvolt-speed2 = <820000>;
+ };
+
+ opp@816000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <816000000>;
+
+ opp-microvolt-speed0 = <880000>;
+ opp-microvolt-speed1 = <820000>;
+ opp-microvolt-speed2 = <820000>;
+ };
+
+ opp@888000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <888000000>;
+
+ opp-microvolt-speed0 = <880000>;
+ opp-microvolt-speed1 = <820000>;
+ opp-microvolt-speed2 = <820000>;
+ };
+
+ opp@1080000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <1080000000>;
+
+ opp-microvolt-speed0 = <940000>;
+ opp-microvolt-speed1 = <880000>;
+ opp-microvolt-speed2 = <880000>;
+ };
+
+ opp@1320000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <1320000000>;
+
+ opp-microvolt-speed0 = <1000000>;
+ opp-microvolt-speed1 = <940000>;
+ opp-microvolt-speed2 = <940000>;
+ };
+
+ opp@1488000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <1488000000>;
+
+ opp-microvolt-speed0 = <1060000>;
+ opp-microvolt-speed1 = <1000000>;
+ opp-microvolt-speed2 = <1000000>;
+ };
+
+ opp@1608000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <1608000000>;
+
+ opp-microvolt-speed0 = <1090000>;
+ opp-microvolt-speed1 = <1030000>;
+ opp-microvolt-speed2 = <1030000>;
+ };
+
+ opp@1704000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <1704000000>;
+
+ opp-microvolt-speed0 = <1120000>;
+ opp-microvolt-speed1 = <1060000>;
+ opp-microvolt-speed2 = <1060000>;
+ };
+
+ opp@1800000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <1800000000>;
+
+ opp-microvolt-speed0 = <1160000>;
+ opp-microvolt-speed1 = <1100000>;
+ opp-microvolt-speed2 = <1100000>;
+ };
+ };
+};
+
+&cpu0 {
+ operating-points-v2 = <&cpu_opp_table>;
+ #cooling-cells = <2>;
+};
+
+&cpu1 {
+ operating-points-v2 = <&cpu_opp_table>;
+ #cooling-cells = <2>;
+};
+
+&cpu2 {
+ operating-points-v2 = <&cpu_opp_table>;
+ #cooling-cells = <2>;
+};
+
+&cpu3 {
+ operating-points-v2 = <&cpu_opp_table>;
+ #cooling-cells = <2>;
+};
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index 60da1627772b..83e32f9c4977 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -258,6 +258,10 @@
ths_calibration: thermal-sensor-calibration@14 {
reg = <0x14 0x8>;
};
+
+ cpu_speed_grade: cpu-speed-grade@1c {
+ reg = <0x1c 0x4>;
+ };
};
watchdog: watchdog@30090a0 {
--
2.20.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-04-19 13:50 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-19 13:50 [PATCH v3 0/7] Add support for Allwinner H6 DVFS Clément Péron
2020-04-19 13:50 ` Clément Péron
2020-04-19 13:50 ` Clément Péron [this message]
2020-04-19 13:50 ` [PATCH v3 1/7] arm64: dts: allwinner: h6: Add CPU Operating Performance Points table Clément Péron
2020-04-19 13:50 ` [PATCH v3 2/7] arm64: configs: Enable sun50i cpufreq nvmem Clément Péron
2020-04-19 13:50 ` Clément Péron
2020-04-19 13:50 ` [PATCH v3 3/7] arm64: dts: allwinner: h6: Enable CPU opp tables for Beelink GS1 Clément Péron
2020-04-19 13:50 ` Clément Péron
2020-04-19 13:50 ` [PATCH v3 4/7] arm64: dts: allwinner: h6: Enable CPU opp tables for Orange Pi 3 Clément Péron
2020-04-19 13:50 ` Clément Péron
2020-04-19 13:50 ` [PATCH v3 5/7] arm64: dts: allwinner: h6: Enable CPU opp tables for Tanix TX6 Clément Péron
2020-04-19 13:50 ` Clément Péron
2020-04-19 13:50 ` [PATCH v3 6/7] arm64: dts: allwinner: Sort Pine H64 device-tree nodes Clément Péron
2020-04-19 13:50 ` Clément Péron
2020-04-19 13:50 ` [PATCH v3 7/7] arm64: dts: allwinner: h6: Enable CPU and GPU opp tables for Pine H64 Clément Péron
2020-04-19 13:50 ` Clément Péron
2020-04-20 8:45 ` [PATCH v3 0/7] Add support for Allwinner H6 DVFS Maxime Ripard
2020-04-20 8:45 ` Maxime Ripard
2020-04-20 10:39 ` Ondřej Jirman
2020-04-20 10:39 ` Ondřej Jirman
2020-04-20 12:36 ` Clément Péron
2020-04-20 12:36 ` Clément Péron
2020-04-20 12:47 ` Maxime Ripard
2020-04-20 12:47 ` Maxime Ripard
2020-04-20 12:49 ` Clément Péron
2020-04-20 12:49 ` Clément Péron
2020-04-20 9:48 ` [linux-sunxi] " Ondřej Jirman
2020-04-20 9:48 ` Ondřej Jirman
2020-04-20 10:27 ` Ondřej Jirman
2020-04-20 10:27 ` Ondřej Jirman
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