From: Marc Zyngier <maz@kernel.org>
To: Andrew Scull <ascull@google.com>
Cc: linux-arm-kernel@lists.infradead.org,
kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org,
Will Deacon <will@kernel.org>,
Andre Przywara <andre.przywara@arm.com>,
Dave Martin <Dave.Martin@arm.com>,
George Cherian <gcherian@marvell.com>,
"Zengtao (B)" <prime.zeng@hisilicon.com>,
Catalin Marinas <catalin.marinas@arm.com>
Subject: Re: [PATCH 06/26] arm64: Add level-hinted TLB invalidation helper
Date: Wed, 6 May 2020 09:05:44 +0100 [thread overview]
Message-ID: <20200506090544.18620ed4@why> (raw)
In-Reply-To: <20200505171631.GC237572@google.com>
On Tue, 5 May 2020 18:16:31 +0100
Andrew Scull <ascull@google.com> wrote:
Hi Andrew,
> > +#define __tlbi_level(op, addr, level) \
> > + do { \
> > + u64 arg = addr; \
> > + \
> > + if (cpus_have_const_cap(ARM64_HAS_ARMv8_4_TTL) && \
> > + level) { \
> > + u64 ttl = level; \
> > + \
> > + switch (PAGE_SIZE) { \
> > + case SZ_4K: \
> > + ttl |= 1 << 2; \
> > + break; \
> > + case SZ_16K: \
> > + ttl |= 2 << 2; \
> > + break; \
> > + case SZ_64K: \
> > + ttl |= 3 << 2; \
> > + break; \
> > + } \
> > + \
> > + arg &= ~TLBI_TTL_MASK; \
> > + arg |= FIELD_PREP(TLBI_TTL_MASK, ttl); \
>
> Despite the spec saying both tables apply to TLB maintenance
> instructions that do not apply to a range of addresses I think it only
> means the 4-bit version (bug report to Arm, or I'm on the wrong spec).
I'm not quite sure what you mean by the 4-bit version here. Do you mean
the instructions taking a VA or IPA as input address? In this case,
yes, this macro is solely for the use of the invalidation of a given
translation, identified by a VA/IPA and a level (which is an implicit
TLB size for a given translation granule).
And yes, it looks like there is a bad copy-paste bug in the ARM ARM
(Rev F.a).
> This is consistent with Table D5-53 and the macro takes a single address
> argument to make misuse with range based tlbi less likely.
>
> It relies on the caller to get the level right and getting it wrong
> could be pretty bad as the spec says all bets are off in that case. Is
> it worth adding a check of the level against the address (seems a bit
> involved), or that it is just 2 bits or adding a short doc comment to
> explain it?
I'd like to avoid checking code at that level, to be honest. If you are
writing TLB invalidation code, you'd better know what you are doing.
Happy to document it a bit more thoroughly though, and set the
expectations that if you misuse the level, you're in for a treat.
> (Looks like we get some constants for the levels in a later patch that
> could be referenced with some form of time travel)
I'm happy to bring these definitions forward, maybe in a more generic
form (they are very S2-specific at the moment).
>
> > + } \
> > + \
> > + __tlbi(op, arg); \
>
> cosmetic nit: double space in here
Well spotted.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
WARNING: multiple messages have this Message-ID (diff)
From: Marc Zyngier <maz@kernel.org>
To: Andrew Scull <ascull@google.com>
Cc: kvm@vger.kernel.org, Andre Przywara <andre.przywara@arm.com>,
kvmarm@lists.cs.columbia.edu,
George Cherian <gcherian@marvell.com>,
"Zengtao \(B\)" <prime.zeng@hisilicon.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>, Dave Martin <Dave.Martin@arm.com>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 06/26] arm64: Add level-hinted TLB invalidation helper
Date: Wed, 6 May 2020 09:05:44 +0100 [thread overview]
Message-ID: <20200506090544.18620ed4@why> (raw)
In-Reply-To: <20200505171631.GC237572@google.com>
On Tue, 5 May 2020 18:16:31 +0100
Andrew Scull <ascull@google.com> wrote:
Hi Andrew,
> > +#define __tlbi_level(op, addr, level) \
> > + do { \
> > + u64 arg = addr; \
> > + \
> > + if (cpus_have_const_cap(ARM64_HAS_ARMv8_4_TTL) && \
> > + level) { \
> > + u64 ttl = level; \
> > + \
> > + switch (PAGE_SIZE) { \
> > + case SZ_4K: \
> > + ttl |= 1 << 2; \
> > + break; \
> > + case SZ_16K: \
> > + ttl |= 2 << 2; \
> > + break; \
> > + case SZ_64K: \
> > + ttl |= 3 << 2; \
> > + break; \
> > + } \
> > + \
> > + arg &= ~TLBI_TTL_MASK; \
> > + arg |= FIELD_PREP(TLBI_TTL_MASK, ttl); \
>
> Despite the spec saying both tables apply to TLB maintenance
> instructions that do not apply to a range of addresses I think it only
> means the 4-bit version (bug report to Arm, or I'm on the wrong spec).
I'm not quite sure what you mean by the 4-bit version here. Do you mean
the instructions taking a VA or IPA as input address? In this case,
yes, this macro is solely for the use of the invalidation of a given
translation, identified by a VA/IPA and a level (which is an implicit
TLB size for a given translation granule).
And yes, it looks like there is a bad copy-paste bug in the ARM ARM
(Rev F.a).
> This is consistent with Table D5-53 and the macro takes a single address
> argument to make misuse with range based tlbi less likely.
>
> It relies on the caller to get the level right and getting it wrong
> could be pretty bad as the spec says all bets are off in that case. Is
> it worth adding a check of the level against the address (seems a bit
> involved), or that it is just 2 bits or adding a short doc comment to
> explain it?
I'd like to avoid checking code at that level, to be honest. If you are
writing TLB invalidation code, you'd better know what you are doing.
Happy to document it a bit more thoroughly though, and set the
expectations that if you misuse the level, you're in for a treat.
> (Looks like we get some constants for the levels in a later patch that
> could be referenced with some form of time travel)
I'm happy to bring these definitions forward, maybe in a more generic
form (they are very S2-specific at the moment).
>
> > + } \
> > + \
> > + __tlbi(op, arg); \
>
> cosmetic nit: double space in here
Well spotted.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
_______________________________________________
kvmarm mailing list
kvmarm@lists.cs.columbia.edu
https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
WARNING: multiple messages have this Message-ID (diff)
From: Marc Zyngier <maz@kernel.org>
To: Andrew Scull <ascull@google.com>
Cc: kvm@vger.kernel.org, Andre Przywara <andre.przywara@arm.com>,
kvmarm@lists.cs.columbia.edu,
George Cherian <gcherian@marvell.com>,
"Zengtao \(B\)" <prime.zeng@hisilicon.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>, Dave Martin <Dave.Martin@arm.com>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 06/26] arm64: Add level-hinted TLB invalidation helper
Date: Wed, 6 May 2020 09:05:44 +0100 [thread overview]
Message-ID: <20200506090544.18620ed4@why> (raw)
In-Reply-To: <20200505171631.GC237572@google.com>
On Tue, 5 May 2020 18:16:31 +0100
Andrew Scull <ascull@google.com> wrote:
Hi Andrew,
> > +#define __tlbi_level(op, addr, level) \
> > + do { \
> > + u64 arg = addr; \
> > + \
> > + if (cpus_have_const_cap(ARM64_HAS_ARMv8_4_TTL) && \
> > + level) { \
> > + u64 ttl = level; \
> > + \
> > + switch (PAGE_SIZE) { \
> > + case SZ_4K: \
> > + ttl |= 1 << 2; \
> > + break; \
> > + case SZ_16K: \
> > + ttl |= 2 << 2; \
> > + break; \
> > + case SZ_64K: \
> > + ttl |= 3 << 2; \
> > + break; \
> > + } \
> > + \
> > + arg &= ~TLBI_TTL_MASK; \
> > + arg |= FIELD_PREP(TLBI_TTL_MASK, ttl); \
>
> Despite the spec saying both tables apply to TLB maintenance
> instructions that do not apply to a range of addresses I think it only
> means the 4-bit version (bug report to Arm, or I'm on the wrong spec).
I'm not quite sure what you mean by the 4-bit version here. Do you mean
the instructions taking a VA or IPA as input address? In this case,
yes, this macro is solely for the use of the invalidation of a given
translation, identified by a VA/IPA and a level (which is an implicit
TLB size for a given translation granule).
And yes, it looks like there is a bad copy-paste bug in the ARM ARM
(Rev F.a).
> This is consistent with Table D5-53 and the macro takes a single address
> argument to make misuse with range based tlbi less likely.
>
> It relies on the caller to get the level right and getting it wrong
> could be pretty bad as the spec says all bets are off in that case. Is
> it worth adding a check of the level against the address (seems a bit
> involved), or that it is just 2 bits or adding a short doc comment to
> explain it?
I'd like to avoid checking code at that level, to be honest. If you are
writing TLB invalidation code, you'd better know what you are doing.
Happy to document it a bit more thoroughly though, and set the
expectations that if you misuse the level, you're in for a treat.
> (Looks like we get some constants for the levels in a later patch that
> could be referenced with some form of time travel)
I'm happy to bring these definitions forward, maybe in a more generic
form (they are very S2-specific at the moment).
>
> > + } \
> > + \
> > + __tlbi(op, arg); \
>
> cosmetic nit: double space in here
Well spotted.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-05-06 8:05 UTC|newest]
Thread overview: 234+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-22 12:00 [PATCH 00/26] KVM: arm64: Preliminary NV patches Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-22 12:00 ` [PATCH 01/26] KVM: arm64: Check advertised Stage-2 page size capability Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-22 13:40 ` Suzuki K Poulose
2020-04-22 13:40 ` Suzuki K Poulose
2020-04-22 13:40 ` Suzuki K Poulose
2020-04-22 14:07 ` Marc Zyngier
2020-04-22 14:07 ` Marc Zyngier
2020-04-22 14:07 ` Marc Zyngier
2020-04-22 14:14 ` Suzuki K Poulose
2020-04-22 14:14 ` Suzuki K Poulose
2020-04-22 14:14 ` Suzuki K Poulose
2020-05-07 11:42 ` Alexandru Elisei
2020-05-07 11:42 ` Alexandru Elisei
2020-05-07 11:42 ` Alexandru Elisei
2020-04-22 12:00 ` [PATCH 02/26] KVM: arm64: Move __load_guest_stage2 to kvm_mmu.h Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-22 13:51 ` Suzuki K Poulose
2020-04-22 13:51 ` Suzuki K Poulose
2020-04-22 13:51 ` Suzuki K Poulose
2020-04-22 13:59 ` Marc Zyngier
2020-04-22 13:59 ` Marc Zyngier
2020-04-22 13:59 ` Marc Zyngier
2020-04-22 12:00 ` [PATCH 03/26] KVM: arm64: Factor out stage 2 page table data from struct kvm Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-05-05 15:26 ` Andrew Scull
2020-05-05 15:26 ` Andrew Scull
2020-05-05 15:26 ` Andrew Scull
2020-05-05 16:32 ` Marc Zyngier
2020-05-05 16:32 ` Marc Zyngier
2020-05-05 16:32 ` Marc Zyngier
2020-05-05 17:23 ` Andrew Scull
2020-05-05 17:23 ` Andrew Scull
2020-05-05 17:23 ` Andrew Scull
2020-05-05 18:10 ` Marc Zyngier
2020-05-05 18:10 ` Marc Zyngier
2020-05-05 18:10 ` Marc Zyngier
2020-05-05 16:03 ` James Morse
2020-05-05 16:03 ` James Morse
2020-05-05 16:03 ` James Morse
2020-05-05 17:59 ` Marc Zyngier
2020-05-05 17:59 ` Marc Zyngier
2020-05-05 17:59 ` Marc Zyngier
2020-05-06 9:30 ` Marc Zyngier
2020-05-06 9:30 ` Marc Zyngier
2020-05-06 9:30 ` Marc Zyngier
2020-05-11 16:38 ` Alexandru Elisei
2020-05-11 16:38 ` Alexandru Elisei
2020-05-11 16:38 ` Alexandru Elisei
2020-05-12 11:17 ` James Morse
2020-05-12 11:17 ` James Morse
2020-05-12 11:17 ` James Morse
2020-05-12 15:47 ` Alexandru Elisei
2020-05-12 15:47 ` Alexandru Elisei
2020-05-12 15:47 ` Alexandru Elisei
2020-05-12 16:13 ` James Morse
2020-05-12 16:13 ` James Morse
2020-05-12 16:13 ` James Morse
2020-05-12 16:53 ` Alexandru Elisei
2020-05-12 16:53 ` Alexandru Elisei
2020-05-12 16:53 ` Alexandru Elisei
2020-05-27 8:41 ` Marc Zyngier
2020-05-27 8:41 ` Marc Zyngier
2020-05-27 8:41 ` Marc Zyngier
2020-05-27 8:45 ` Alexandru Elisei
2020-05-27 8:45 ` Alexandru Elisei
2020-05-27 8:45 ` Alexandru Elisei
2020-04-22 12:00 ` [PATCH 04/26] arm64: Detect the ARMv8.4 TTL feature Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-27 15:55 ` Suzuki K Poulose
2020-04-27 15:55 ` Suzuki K Poulose
2020-04-27 15:55 ` Suzuki K Poulose
2020-04-22 12:00 ` [PATCH 05/26] arm64: Document SW reserved PTE/PMD bits in Stage-2 descriptors Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-05-05 15:59 ` Andrew Scull
2020-05-05 15:59 ` Andrew Scull
2020-05-05 15:59 ` Andrew Scull
2020-05-06 9:39 ` Marc Zyngier
2020-05-06 9:39 ` Marc Zyngier
2020-05-06 9:39 ` Marc Zyngier
2020-05-06 10:11 ` Andrew Scull
2020-05-06 10:11 ` Andrew Scull
2020-05-06 10:11 ` Andrew Scull
2020-04-22 12:00 ` [PATCH 06/26] arm64: Add level-hinted TLB invalidation helper Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-05-05 17:16 ` Andrew Scull
2020-05-05 17:16 ` Andrew Scull
2020-05-05 17:16 ` Andrew Scull
2020-05-06 8:05 ` Marc Zyngier [this message]
2020-05-06 8:05 ` Marc Zyngier
2020-05-06 8:05 ` Marc Zyngier
2020-04-22 12:00 ` [PATCH 07/26] KVM: arm64: Add a level hint to __kvm_tlb_flush_vmid_ipa Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-05-07 15:08 ` Andrew Scull
2020-05-07 15:08 ` Andrew Scull
2020-05-07 15:08 ` Andrew Scull
2020-05-07 15:13 ` Marc Zyngier
2020-05-07 15:13 ` Marc Zyngier
2020-05-07 15:13 ` Marc Zyngier
2020-04-22 12:00 ` [PATCH 08/26] KVM: arm64: Use TTL hint in when invalidating stage-2 translations Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-05-07 15:13 ` Andrew Scull
2020-05-07 15:13 ` Andrew Scull
2020-05-07 15:13 ` Andrew Scull
2020-05-12 12:04 ` James Morse
2020-05-12 12:04 ` James Morse
2020-05-12 12:04 ` James Morse
2020-05-13 9:06 ` Andrew Scull
2020-05-13 9:06 ` Andrew Scull
2020-05-13 9:06 ` Andrew Scull
2020-05-27 8:59 ` Marc Zyngier
2020-05-27 8:59 ` Marc Zyngier
2020-05-27 8:59 ` Marc Zyngier
2020-05-12 17:26 ` James Morse
2020-05-12 17:26 ` James Morse
2020-05-12 17:26 ` James Morse
2020-04-22 12:00 ` [PATCH 09/26] KVM: arm64: vgic-v3: Take cpu_if pointer directly instead of vcpu Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-05-07 16:26 ` James Morse
2020-05-07 16:26 ` James Morse
2020-05-07 16:26 ` James Morse
2020-05-08 12:20 ` Marc Zyngier
2020-05-08 12:20 ` Marc Zyngier
2020-05-08 12:20 ` Marc Zyngier
2020-04-22 12:00 ` [PATCH 10/26] KVM: arm64: Refactor vcpu_{read,write}_sys_reg Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-05-26 16:28 ` James Morse
2020-05-26 16:28 ` James Morse
2020-05-26 16:28 ` James Morse
2020-05-27 10:04 ` Marc Zyngier
2020-05-27 10:04 ` Marc Zyngier
2020-05-27 10:04 ` Marc Zyngier
2020-04-22 12:00 ` [PATCH 11/26] KVM: arm64: Add missing reset handlers for PMU emulation Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-05-26 16:29 ` James Morse
2020-05-26 16:29 ` James Morse
2020-05-26 16:29 ` James Morse
2020-04-22 12:00 ` [PATCH 12/26] KVM: arm64: Move sysreg reset check to boot time Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-22 12:00 ` [PATCH 13/26] KVM: arm64: Introduce accessor for ctxt->sys_reg Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-22 12:00 ` [PATCH 14/26] KVM: arm64: hyp: Use ctxt_sys_reg/__vcpu_sys_reg instead of raw sys_regs access Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-22 12:00 ` [PATCH 15/26] KVM: arm64: sve: Use __vcpu_sys_reg() " Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-22 12:00 ` [PATCH 16/26] KVM: arm64: pauth: Use ctxt_sys_reg() " Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-22 12:00 ` [PATCH 17/26] KVM: arm64: debug: " Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-22 12:00 ` [PATCH 18/26] KVM: arm64: Don't use empty structures as CPU reset state Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-24 4:07 ` Zenghui Yu
2020-04-24 4:07 ` Zenghui Yu
2020-04-24 4:07 ` Zenghui Yu
2020-04-24 7:45 ` Marc Zyngier
2020-04-24 7:45 ` Marc Zyngier
2020-04-24 7:45 ` Marc Zyngier
2020-04-28 1:34 ` Zengtao (B)
2020-04-28 1:34 ` Zengtao (B)
2020-04-28 1:34 ` Zengtao (B)
2020-04-22 12:00 ` [PATCH 19/26] KVM: arm64: Make struct kvm_regs userspace-only Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-05-26 16:29 ` James Morse
2020-05-26 16:29 ` James Morse
2020-05-26 16:29 ` James Morse
2020-05-27 10:22 ` Marc Zyngier
2020-05-27 10:22 ` Marc Zyngier
2020-05-27 10:22 ` Marc Zyngier
2020-04-22 12:00 ` [PATCH 20/26] KVM: arm64: Move ELR_EL1 to the system register array Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-05-26 16:29 ` James Morse
2020-05-26 16:29 ` James Morse
2020-05-26 16:29 ` James Morse
2020-05-27 10:36 ` Marc Zyngier
2020-05-27 10:36 ` Marc Zyngier
2020-05-27 10:36 ` Marc Zyngier
2020-04-22 12:00 ` [PATCH 21/26] KVM: arm64: Move SP_EL1 " Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-05-26 16:29 ` James Morse
2020-05-26 16:29 ` James Morse
2020-05-26 16:29 ` James Morse
2020-04-22 12:00 ` [PATCH 22/26] KVM: arm64: Disintegrate SPSR array Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-05-26 16:30 ` James Morse
2020-05-26 16:30 ` James Morse
2020-05-26 16:30 ` James Morse
2020-04-22 12:00 ` [PATCH 23/26] KVM: arm64: Move SPSR_EL1 to the system register array Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-05-26 16:30 ` James Morse
2020-05-26 16:30 ` James Morse
2020-05-26 16:30 ` James Morse
2020-04-22 12:00 ` [PATCH 24/26] KVM: arm64: timers: Rename kvm_timer_sync_hwstate to kvm_timer_sync_user Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-22 12:00 ` [PATCH 25/26] KVM: arm64: timers: Move timer registers to the sys_regs file Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-22 12:00 ` [PATCH 26/26] KVM: arm64: Parametrize exception entry with a target EL Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-05-19 10:44 ` Mark Rutland
2020-05-19 10:44 ` Mark Rutland
2020-05-19 10:44 ` Mark Rutland
2020-05-27 9:34 ` Marc Zyngier
2020-05-27 9:34 ` Marc Zyngier
2020-05-27 9:34 ` Marc Zyngier
2020-05-27 14:41 ` Mark Rutland
2020-05-27 14:41 ` Mark Rutland
2020-05-27 14:41 ` Mark Rutland
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