[PATCH v4 06/14] PCI: cadence: Allow pci_host_bridge to have custom pci_ops

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From: Kishon Vijay Abraham I <kishon@ti.com>
To: Bjorn Helgaas <bhelgaas@google.com>,
	Rob Herring <robh+dt@kernel.org>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Arnd Bergmann <arnd@arndb.de>, Tom Joseph <tjoseph@cadence.com>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	<linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>, <linux-omap@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>, <kishon@ti.com>
Subject: [PATCH v4 06/14] PCI: cadence: Allow pci_host_bridge to have custom pci_ops
Date: Wed, 6 May 2020 20:44:21 +0530	[thread overview]
Message-ID: <20200506151429.12255-7-kishon@ti.com> (raw)
In-Reply-To: <20200506151429.12255-1-kishon@ti.com>

Certain platforms like TI's J721E allows only 32-bit configuration
space access. In such cases pci_generic_config_read and
pci_generic_config_write cannot be used. Add support in Cadence core
to let pci_host_bridge have custom pci_ops.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
 drivers/pci/controller/cadence/pcie-cadence-host.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c
index a60b9627cfbf..6c84520318a7 100644
--- a/drivers/pci/controller/cadence/pcie-cadence-host.c
+++ b/drivers/pci/controller/cadence/pcie-cadence-host.c
@@ -291,7 +291,8 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc)
 	list_splice_init(&resources, &bridge->windows);
 	bridge->dev.parent = dev;
 	bridge->busnr = pcie->bus;
-	bridge->ops = &cdns_pcie_host_ops;
+	if (!bridge->ops)
+		bridge->ops = &cdns_pcie_host_ops;
 	bridge->map_irq = of_irq_parse_and_map_pci;
 	bridge->swizzle_irq = pci_common_swizzle;
 
-- 
2.17.1

WARNING: multiple messages have this Message-ID (diff)

From: Kishon Vijay Abraham I <kishon@ti.com>
To: Bjorn Helgaas <bhelgaas@google.com>,
	Rob Herring <robh+dt@kernel.org>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Arnd Bergmann <arnd@arndb.de>, Tom Joseph <tjoseph@cadence.com>
Cc: devicetree@vger.kernel.org,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	linux-kernel@vger.kernel.org, kishon@ti.com,
	linux-pci@vger.kernel.org, linux-omap@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH v4 06/14] PCI: cadence: Allow pci_host_bridge to have custom pci_ops
Date: Wed, 6 May 2020 20:44:21 +0530	[thread overview]
Message-ID: <20200506151429.12255-7-kishon@ti.com> (raw)
In-Reply-To: <20200506151429.12255-1-kishon@ti.com>

Certain platforms like TI's J721E allows only 32-bit configuration
space access. In such cases pci_generic_config_read and
pci_generic_config_write cannot be used. Add support in Cadence core
to let pci_host_bridge have custom pci_ops.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
 drivers/pci/controller/cadence/pcie-cadence-host.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c
index a60b9627cfbf..6c84520318a7 100644
--- a/drivers/pci/controller/cadence/pcie-cadence-host.c
+++ b/drivers/pci/controller/cadence/pcie-cadence-host.c
@@ -291,7 +291,8 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc)
 	list_splice_init(&resources, &bridge->windows);
 	bridge->dev.parent = dev;
 	bridge->busnr = pcie->bus;
-	bridge->ops = &cdns_pcie_host_ops;
+	if (!bridge->ops)
+		bridge->ops = &cdns_pcie_host_ops;
 	bridge->map_irq = of_irq_parse_and_map_pci;
 	bridge->swizzle_irq = pci_common_swizzle;
 
-- 
2.17.1


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next prev parent reply	other threads:[~2020-05-06 15:15 UTC|newest]

Thread overview: 62+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-06 15:14 [PATCH v4 00/14] Add PCIe support to TI's J721E SoC Kishon Vijay Abraham I
2020-05-06 15:14 ` Kishon Vijay Abraham I
2020-05-06 15:14 ` [PATCH v4 01/14] PCI: cadence: Fix cdns_pcie_{host|ep}_setup() error path Kishon Vijay Abraham I
2020-05-06 15:14   ` Kishon Vijay Abraham I
2020-05-20 20:59   ` Rob Herring
2020-05-20 20:59     ` Rob Herring
2020-05-06 15:14 ` [PATCH v4 02/14] linux/kernel.h: Add PTR_ALIGN_DOWN macro Kishon Vijay Abraham I
2020-05-06 15:14   ` Kishon Vijay Abraham I
2020-05-20 21:00   ` Rob Herring
2020-05-20 21:00     ` Rob Herring
2020-05-06 15:14 ` [PATCH v4 03/14] PCI: cadence: Add support to use custom read and write accessors Kishon Vijay Abraham I
2020-05-06 15:14   ` Kishon Vijay Abraham I
2020-05-20 21:02   ` Rob Herring
2020-05-20 21:02     ` Rob Herring
2020-05-20 22:07   ` Rob Herring
2020-05-20 22:07     ` Rob Herring
2020-05-21 13:33     ` Kishon Vijay Abraham I
2020-05-21 13:33       ` Kishon Vijay Abraham I
2020-05-21 22:17       ` Rob Herring
2020-05-21 22:17         ` Rob Herring
2020-05-22  3:36         ` Kishon Vijay Abraham I
2020-05-22  3:36           ` Kishon Vijay Abraham I
2020-05-06 15:14 ` [PATCH v4 04/14] PCI: cadence: Add support to start link and verify link status Kishon Vijay Abraham I
2020-05-06 15:14   ` Kishon Vijay Abraham I
2020-05-20 21:06   ` Rob Herring
2020-05-20 21:06     ` Rob Herring
2020-05-06 15:14 ` [PATCH v4 05/14] PCI: cadence: Add read/write accessors to perform only 32-bit accesses Kishon Vijay Abraham I
2020-05-06 15:14   ` Kishon Vijay Abraham I
2020-05-06 15:14 ` Kishon Vijay Abraham I [this message]
2020-05-06 15:14   ` [PATCH v4 06/14] PCI: cadence: Allow pci_host_bridge to have custom pci_ops Kishon Vijay Abraham I
2020-05-06 15:14 ` [PATCH v4 07/14] PCI: cadence: Add new *ops* for CPU addr fixup Kishon Vijay Abraham I
2020-05-06 15:14   ` Kishon Vijay Abraham I
2020-05-20 21:34   ` Rob Herring
2020-05-20 21:34     ` Rob Herring
2020-05-21 11:34     ` Kishon Vijay Abraham I
2020-05-21 11:34       ` Kishon Vijay Abraham I
2020-05-22 16:45       ` Rob Herring
2020-05-22 16:45         ` Rob Herring
2020-05-23  1:24         ` Kishon Vijay Abraham I
2020-05-23  1:24           ` Kishon Vijay Abraham I
2020-05-06 15:14 ` [PATCH v4 08/14] PCI: cadence: Fix updating Vendor ID and Subsystem Vendor ID register Kishon Vijay Abraham I
2020-05-06 15:14   ` Kishon Vijay Abraham I
2020-05-20 21:36   ` Rob Herring
2020-05-20 21:36     ` Rob Herring
2020-05-06 15:14 ` [PATCH v4 09/14] PCI: cadence: Add MSI-X support to Endpoint driver Kishon Vijay Abraham I
2020-05-06 15:14   ` Kishon Vijay Abraham I
2020-05-06 15:14 ` [PATCH v4 10/14] dt-bindings: PCI: Add host mode dt-bindings for TI's J721E SoC Kishon Vijay Abraham I
2020-05-06 15:14   ` Kishon Vijay Abraham I
2020-05-06 15:14 ` [PATCH v4 11/14] dt-bindings: PCI: Add EP " Kishon Vijay Abraham I
2020-05-06 15:14   ` Kishon Vijay Abraham I
2020-05-06 15:14 ` [PATCH v4 12/14] PCI: j721e: Add TI J721E PCIe driver Kishon Vijay Abraham I
2020-05-06 15:14   ` Kishon Vijay Abraham I
2020-05-06 15:14 ` [PATCH v4 13/14] misc: pci_endpoint_test: Add J721E in pci_device_id table Kishon Vijay Abraham I
2020-05-06 15:14   ` Kishon Vijay Abraham I
2020-05-20 22:12   ` Rob Herring
2020-05-20 22:12     ` Rob Herring
2020-05-06 15:14 ` [PATCH v4 14/14] MAINTAINERS: Add Kishon Vijay Abraham I for TI J721E SoC PCIe Kishon Vijay Abraham I
2020-05-06 15:14   ` Kishon Vijay Abraham I
2020-05-20 22:12   ` Rob Herring
2020-05-20 22:12     ` Rob Herring
2020-05-18 11:14 ` [PATCH v4 00/14] Add PCIe support to TI's J721E SoC Kishon Vijay Abraham I
2020-05-18 11:14   ` Kishon Vijay Abraham I

find likely ancestor, descendant, or conflicting patches for this message:
dfblob:a60b9627cfb dfblob:a60b9627cfb dfblob:6c84520318a
dfblob:6c84520318a
	(help)

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