From: Boris Brezillon <boris.brezillon@collabora.com>
To: Pratyush Yadav <p.yadav@ti.com>
Cc: Tudor Ambarus <tudor.ambarus@microchip.com>,
Miquel Raynal <miquel.raynal@bootlin.com>,
Richard Weinberger <richard@nod.at>,
Vignesh Raghavendra <vigneshr@ti.com>,
Mark Brown <broonie@kernel.org>,
Nicolas Ferre <nicolas.ferre@microchip.com>,
Alexandre Belloni <alexandre.belloni@bootlin.com>,
Ludovic Desroches <ludovic.desroches@microchip.com>,
Matthias Brugger <matthias.bgg@gmail.com>,
Michal Simek <michal.simek@xilinx.com>,
<linux-mtd@lists.infradead.org>, <linux-kernel@vger.kernel.org>,
<linux-spi@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-mediatek@lists.infradead.org>,
Sekhar Nori <nsekhar@ti.com>,
Mason Yang <masonccyang@mxic.com.tw>
Subject: Re: [PATCH v8 02/19] spi: spi-mem: allow specifying a command's extension
Date: Sun, 24 May 2020 22:17:58 +0200 [thread overview]
Message-ID: <20200524221758.7c30f336@collabora.com> (raw)
In-Reply-To: <20200522224042.29970-3-p.yadav@ti.com>
On Sat, 23 May 2020 04:10:25 +0530
Pratyush Yadav <p.yadav@ti.com> wrote:
> diff --git a/drivers/spi/spi-mxic.c b/drivers/spi/spi-mxic.c
> index 69491f3a515d..4e4292f0ee1d 100644
> --- a/drivers/spi/spi-mxic.c
> +++ b/drivers/spi/spi-mxic.c
> @@ -356,6 +356,7 @@ static int mxic_spi_mem_exec_op(struct spi_mem *mem,
> int nio = 1, i, ret;
> u32 ss_ctrl;
> u8 addr[8];
> + u8 opcode = op->cmd.opcode & 0xff;
You don't need the '& 0xff' here, the cast to an u8 will truncate the
value anyway.
>
> ret = mxic_spi_set_freq(mxic, mem->spi->max_speed_hz);
> if (ret)
> @@ -393,7 +394,7 @@ static int mxic_spi_mem_exec_op(struct spi_mem *mem,
> writel(readl(mxic->regs + HC_CFG) | HC_CFG_MAN_CS_ASSERT,
> mxic->regs + HC_CFG);
>
> - ret = mxic_spi_data_xfer(mxic, &op->cmd.opcode, NULL, 1);
> + ret = mxic_spi_data_xfer(mxic, &opcode, NULL, 1);
> if (ret)
> goto out;
>
> diff --git a/drivers/spi/spi-zynq-qspi.c b/drivers/spi/spi-zynq-qspi.c
> index 17641157354d..41389856e14a 100644
> --- a/drivers/spi/spi-zynq-qspi.c
> +++ b/drivers/spi/spi-zynq-qspi.c
> @@ -527,20 +527,21 @@ static int zynq_qspi_exec_mem_op(struct spi_mem *mem,
> struct zynq_qspi *xqspi = spi_controller_get_devdata(mem->spi->master);
> int err = 0, i;
> u8 *tmpbuf;
> + u8 opcode = op->cmd.opcode & 0xff;
>
Ditto.
> dev_dbg(xqspi->dev, "cmd:%#x mode:%d.%d.%d.%d\n",
> - op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
> + opcode, op->cmd.buswidth, op->addr.buswidth,
> op->dummy.buswidth, op->data.buswidth);
>
> zynq_qspi_chipselect(mem->spi, true);
> zynq_qspi_config_op(xqspi, mem->spi);
>
> - if (op->cmd.opcode) {
> + if (opcode) {
Unrelated to this patch, but this test is wrong. I don't see why we
couldn't have a '0' opcode. The test should be dropped or done on the
new op->cmd.nbytes field.
> reinit_completion(&xqspi->data_completion);
> - xqspi->txbuf = (u8 *)&op->cmd.opcode;
> + xqspi->txbuf = &opcode;
> xqspi->rxbuf = NULL;
> - xqspi->tx_bytes = sizeof(op->cmd.opcode);
> - xqspi->rx_bytes = sizeof(op->cmd.opcode);
> + xqspi->tx_bytes = op->cmd.nbytes;
> + xqspi->rx_bytes = op->cmd.nbytes;
> zynq_qspi_write_op(xqspi, ZYNQ_QSPI_FIFO_DEPTH, true);
> zynq_qspi_write(xqspi, ZYNQ_QSPI_IEN_OFFSET,
> ZYNQ_QSPI_IXR_RXTX_MASK);
WARNING: multiple messages have this Message-ID (diff)
From: Boris Brezillon <boris.brezillon@collabora.com>
To: Pratyush Yadav <p.yadav@ti.com>
Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>,
Mason Yang <masonccyang@mxic.com.tw>,
Vignesh Raghavendra <vigneshr@ti.com>,
Tudor Ambarus <tudor.ambarus@microchip.com>,
Richard Weinberger <richard@nod.at>, Sekhar Nori <nsekhar@ti.com>,
Nicolas Ferre <nicolas.ferre@microchip.com>,
Michal Simek <michal.simek@xilinx.com>,
Ludovic Desroches <ludovic.desroches@microchip.com>,
Mark Brown <broonie@kernel.org>,
linux-mtd@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
Miquel Raynal <miquel.raynal@bootlin.com>,
Matthias Brugger <matthias.bgg@gmail.com>,
linux-mediatek@lists.infradead.org, linux-spi@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v8 02/19] spi: spi-mem: allow specifying a command's extension
Date: Sun, 24 May 2020 22:17:58 +0200 [thread overview]
Message-ID: <20200524221758.7c30f336@collabora.com> (raw)
In-Reply-To: <20200522224042.29970-3-p.yadav@ti.com>
On Sat, 23 May 2020 04:10:25 +0530
Pratyush Yadav <p.yadav@ti.com> wrote:
> diff --git a/drivers/spi/spi-mxic.c b/drivers/spi/spi-mxic.c
> index 69491f3a515d..4e4292f0ee1d 100644
> --- a/drivers/spi/spi-mxic.c
> +++ b/drivers/spi/spi-mxic.c
> @@ -356,6 +356,7 @@ static int mxic_spi_mem_exec_op(struct spi_mem *mem,
> int nio = 1, i, ret;
> u32 ss_ctrl;
> u8 addr[8];
> + u8 opcode = op->cmd.opcode & 0xff;
You don't need the '& 0xff' here, the cast to an u8 will truncate the
value anyway.
>
> ret = mxic_spi_set_freq(mxic, mem->spi->max_speed_hz);
> if (ret)
> @@ -393,7 +394,7 @@ static int mxic_spi_mem_exec_op(struct spi_mem *mem,
> writel(readl(mxic->regs + HC_CFG) | HC_CFG_MAN_CS_ASSERT,
> mxic->regs + HC_CFG);
>
> - ret = mxic_spi_data_xfer(mxic, &op->cmd.opcode, NULL, 1);
> + ret = mxic_spi_data_xfer(mxic, &opcode, NULL, 1);
> if (ret)
> goto out;
>
> diff --git a/drivers/spi/spi-zynq-qspi.c b/drivers/spi/spi-zynq-qspi.c
> index 17641157354d..41389856e14a 100644
> --- a/drivers/spi/spi-zynq-qspi.c
> +++ b/drivers/spi/spi-zynq-qspi.c
> @@ -527,20 +527,21 @@ static int zynq_qspi_exec_mem_op(struct spi_mem *mem,
> struct zynq_qspi *xqspi = spi_controller_get_devdata(mem->spi->master);
> int err = 0, i;
> u8 *tmpbuf;
> + u8 opcode = op->cmd.opcode & 0xff;
>
Ditto.
> dev_dbg(xqspi->dev, "cmd:%#x mode:%d.%d.%d.%d\n",
> - op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
> + opcode, op->cmd.buswidth, op->addr.buswidth,
> op->dummy.buswidth, op->data.buswidth);
>
> zynq_qspi_chipselect(mem->spi, true);
> zynq_qspi_config_op(xqspi, mem->spi);
>
> - if (op->cmd.opcode) {
> + if (opcode) {
Unrelated to this patch, but this test is wrong. I don't see why we
couldn't have a '0' opcode. The test should be dropped or done on the
new op->cmd.nbytes field.
> reinit_completion(&xqspi->data_completion);
> - xqspi->txbuf = (u8 *)&op->cmd.opcode;
> + xqspi->txbuf = &opcode;
> xqspi->rxbuf = NULL;
> - xqspi->tx_bytes = sizeof(op->cmd.opcode);
> - xqspi->rx_bytes = sizeof(op->cmd.opcode);
> + xqspi->tx_bytes = op->cmd.nbytes;
> + xqspi->rx_bytes = op->cmd.nbytes;
> zynq_qspi_write_op(xqspi, ZYNQ_QSPI_FIFO_DEPTH, true);
> zynq_qspi_write(xqspi, ZYNQ_QSPI_IEN_OFFSET,
> ZYNQ_QSPI_IXR_RXTX_MASK);
______________________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-mtd/
WARNING: multiple messages have this Message-ID (diff)
From: Boris Brezillon <boris.brezillon@collabora.com>
To: Pratyush Yadav <p.yadav@ti.com>
Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>,
Mason Yang <masonccyang@mxic.com.tw>,
Vignesh Raghavendra <vigneshr@ti.com>,
Tudor Ambarus <tudor.ambarus@microchip.com>,
Richard Weinberger <richard@nod.at>, Sekhar Nori <nsekhar@ti.com>,
Nicolas Ferre <nicolas.ferre@microchip.com>,
Michal Simek <michal.simek@xilinx.com>,
Ludovic Desroches <ludovic.desroches@microchip.com>,
Mark Brown <broonie@kernel.org>,
linux-mtd@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
Miquel Raynal <miquel.raynal@bootlin.com>,
Matthias Brugger <matthias.bgg@gmail.com>,
linux-mediatek@lists.infradead.org, linux-spi@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v8 02/19] spi: spi-mem: allow specifying a command's extension
Date: Sun, 24 May 2020 22:17:58 +0200 [thread overview]
Message-ID: <20200524221758.7c30f336@collabora.com> (raw)
In-Reply-To: <20200522224042.29970-3-p.yadav@ti.com>
On Sat, 23 May 2020 04:10:25 +0530
Pratyush Yadav <p.yadav@ti.com> wrote:
> diff --git a/drivers/spi/spi-mxic.c b/drivers/spi/spi-mxic.c
> index 69491f3a515d..4e4292f0ee1d 100644
> --- a/drivers/spi/spi-mxic.c
> +++ b/drivers/spi/spi-mxic.c
> @@ -356,6 +356,7 @@ static int mxic_spi_mem_exec_op(struct spi_mem *mem,
> int nio = 1, i, ret;
> u32 ss_ctrl;
> u8 addr[8];
> + u8 opcode = op->cmd.opcode & 0xff;
You don't need the '& 0xff' here, the cast to an u8 will truncate the
value anyway.
>
> ret = mxic_spi_set_freq(mxic, mem->spi->max_speed_hz);
> if (ret)
> @@ -393,7 +394,7 @@ static int mxic_spi_mem_exec_op(struct spi_mem *mem,
> writel(readl(mxic->regs + HC_CFG) | HC_CFG_MAN_CS_ASSERT,
> mxic->regs + HC_CFG);
>
> - ret = mxic_spi_data_xfer(mxic, &op->cmd.opcode, NULL, 1);
> + ret = mxic_spi_data_xfer(mxic, &opcode, NULL, 1);
> if (ret)
> goto out;
>
> diff --git a/drivers/spi/spi-zynq-qspi.c b/drivers/spi/spi-zynq-qspi.c
> index 17641157354d..41389856e14a 100644
> --- a/drivers/spi/spi-zynq-qspi.c
> +++ b/drivers/spi/spi-zynq-qspi.c
> @@ -527,20 +527,21 @@ static int zynq_qspi_exec_mem_op(struct spi_mem *mem,
> struct zynq_qspi *xqspi = spi_controller_get_devdata(mem->spi->master);
> int err = 0, i;
> u8 *tmpbuf;
> + u8 opcode = op->cmd.opcode & 0xff;
>
Ditto.
> dev_dbg(xqspi->dev, "cmd:%#x mode:%d.%d.%d.%d\n",
> - op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
> + opcode, op->cmd.buswidth, op->addr.buswidth,
> op->dummy.buswidth, op->data.buswidth);
>
> zynq_qspi_chipselect(mem->spi, true);
> zynq_qspi_config_op(xqspi, mem->spi);
>
> - if (op->cmd.opcode) {
> + if (opcode) {
Unrelated to this patch, but this test is wrong. I don't see why we
couldn't have a '0' opcode. The test should be dropped or done on the
new op->cmd.nbytes field.
> reinit_completion(&xqspi->data_completion);
> - xqspi->txbuf = (u8 *)&op->cmd.opcode;
> + xqspi->txbuf = &opcode;
> xqspi->rxbuf = NULL;
> - xqspi->tx_bytes = sizeof(op->cmd.opcode);
> - xqspi->rx_bytes = sizeof(op->cmd.opcode);
> + xqspi->tx_bytes = op->cmd.nbytes;
> + xqspi->rx_bytes = op->cmd.nbytes;
> zynq_qspi_write_op(xqspi, ZYNQ_QSPI_FIFO_DEPTH, true);
> zynq_qspi_write(xqspi, ZYNQ_QSPI_IEN_OFFSET,
> ZYNQ_QSPI_IXR_RXTX_MASK);
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
WARNING: multiple messages have this Message-ID (diff)
From: Boris Brezillon <boris.brezillon@collabora.com>
To: Pratyush Yadav <p.yadav@ti.com>
Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>,
Mason Yang <masonccyang@mxic.com.tw>,
Vignesh Raghavendra <vigneshr@ti.com>,
Tudor Ambarus <tudor.ambarus@microchip.com>,
Richard Weinberger <richard@nod.at>, Sekhar Nori <nsekhar@ti.com>,
Michal Simek <michal.simek@xilinx.com>,
Ludovic Desroches <ludovic.desroches@microchip.com>,
Mark Brown <broonie@kernel.org>,
linux-mtd@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
Miquel Raynal <miquel.raynal@bootlin.com>,
Matthias Brugger <matthias.bgg@gmail.com>,
linux-mediatek@lists.infradead.org, linux-spi@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v8 02/19] spi: spi-mem: allow specifying a command's extension
Date: Sun, 24 May 2020 22:17:58 +0200 [thread overview]
Message-ID: <20200524221758.7c30f336@collabora.com> (raw)
In-Reply-To: <20200522224042.29970-3-p.yadav@ti.com>
On Sat, 23 May 2020 04:10:25 +0530
Pratyush Yadav <p.yadav@ti.com> wrote:
> diff --git a/drivers/spi/spi-mxic.c b/drivers/spi/spi-mxic.c
> index 69491f3a515d..4e4292f0ee1d 100644
> --- a/drivers/spi/spi-mxic.c
> +++ b/drivers/spi/spi-mxic.c
> @@ -356,6 +356,7 @@ static int mxic_spi_mem_exec_op(struct spi_mem *mem,
> int nio = 1, i, ret;
> u32 ss_ctrl;
> u8 addr[8];
> + u8 opcode = op->cmd.opcode & 0xff;
You don't need the '& 0xff' here, the cast to an u8 will truncate the
value anyway.
>
> ret = mxic_spi_set_freq(mxic, mem->spi->max_speed_hz);
> if (ret)
> @@ -393,7 +394,7 @@ static int mxic_spi_mem_exec_op(struct spi_mem *mem,
> writel(readl(mxic->regs + HC_CFG) | HC_CFG_MAN_CS_ASSERT,
> mxic->regs + HC_CFG);
>
> - ret = mxic_spi_data_xfer(mxic, &op->cmd.opcode, NULL, 1);
> + ret = mxic_spi_data_xfer(mxic, &opcode, NULL, 1);
> if (ret)
> goto out;
>
> diff --git a/drivers/spi/spi-zynq-qspi.c b/drivers/spi/spi-zynq-qspi.c
> index 17641157354d..41389856e14a 100644
> --- a/drivers/spi/spi-zynq-qspi.c
> +++ b/drivers/spi/spi-zynq-qspi.c
> @@ -527,20 +527,21 @@ static int zynq_qspi_exec_mem_op(struct spi_mem *mem,
> struct zynq_qspi *xqspi = spi_controller_get_devdata(mem->spi->master);
> int err = 0, i;
> u8 *tmpbuf;
> + u8 opcode = op->cmd.opcode & 0xff;
>
Ditto.
> dev_dbg(xqspi->dev, "cmd:%#x mode:%d.%d.%d.%d\n",
> - op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
> + opcode, op->cmd.buswidth, op->addr.buswidth,
> op->dummy.buswidth, op->data.buswidth);
>
> zynq_qspi_chipselect(mem->spi, true);
> zynq_qspi_config_op(xqspi, mem->spi);
>
> - if (op->cmd.opcode) {
> + if (opcode) {
Unrelated to this patch, but this test is wrong. I don't see why we
couldn't have a '0' opcode. The test should be dropped or done on the
new op->cmd.nbytes field.
> reinit_completion(&xqspi->data_completion);
> - xqspi->txbuf = (u8 *)&op->cmd.opcode;
> + xqspi->txbuf = &opcode;
> xqspi->rxbuf = NULL;
> - xqspi->tx_bytes = sizeof(op->cmd.opcode);
> - xqspi->rx_bytes = sizeof(op->cmd.opcode);
> + xqspi->tx_bytes = op->cmd.nbytes;
> + xqspi->rx_bytes = op->cmd.nbytes;
> zynq_qspi_write_op(xqspi, ZYNQ_QSPI_FIFO_DEPTH, true);
> zynq_qspi_write(xqspi, ZYNQ_QSPI_IEN_OFFSET,
> ZYNQ_QSPI_IXR_RXTX_MASK);
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next prev parent reply other threads:[~2020-05-24 20:18 UTC|newest]
Thread overview: 84+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-22 22:40 [PATCH v8 00/19] mtd: spi-nor: add xSPI Octal DTR support Pratyush Yadav
2020-05-22 22:40 ` Pratyush Yadav
2020-05-22 22:40 ` Pratyush Yadav
2020-05-22 22:40 ` Pratyush Yadav
2020-05-22 22:40 ` [PATCH v8 01/19] spi: spi-mem: allow specifying whether an op is DTR or not Pratyush Yadav
2020-05-22 22:40 ` Pratyush Yadav
2020-05-22 22:40 ` Pratyush Yadav
2020-05-22 22:40 ` Pratyush Yadav
2020-05-22 22:40 ` [PATCH v8 02/19] spi: spi-mem: allow specifying a command's extension Pratyush Yadav
2020-05-22 22:40 ` Pratyush Yadav
2020-05-22 22:40 ` Pratyush Yadav
2020-05-22 22:40 ` Pratyush Yadav
2020-05-24 20:17 ` Boris Brezillon [this message]
2020-05-24 20:17 ` Boris Brezillon
2020-05-24 20:17 ` Boris Brezillon
2020-05-24 20:17 ` Boris Brezillon
2020-05-22 22:40 ` [PATCH v8 03/19] spi: atmel-quadspi: reject DTR ops Pratyush Yadav
2020-05-22 22:40 ` Pratyush Yadav
2020-05-22 22:40 ` Pratyush Yadav
2020-05-22 22:40 ` Pratyush Yadav
2020-05-22 22:40 ` [PATCH v8 04/19] spi: spi-mtk-nor: " Pratyush Yadav
2020-05-22 22:40 ` Pratyush Yadav
2020-05-22 22:40 ` Pratyush Yadav
2020-05-22 22:40 ` Pratyush Yadav
2020-05-22 22:40 ` [PATCH v8 05/19] mtd: spi-nor: add support for DTR protocol Pratyush Yadav
2020-05-22 22:40 ` Pratyush Yadav
2020-05-22 22:40 ` Pratyush Yadav
2020-05-22 22:40 ` Pratyush Yadav
2020-05-22 22:40 ` [PATCH v8 06/19] mtd: spi-nor: sfdp: default to addr_width of 3 for configurable widths Pratyush Yadav
2020-05-22 22:40 ` Pratyush Yadav
2020-05-22 22:40 ` Pratyush Yadav
2020-05-22 22:40 ` Pratyush Yadav
2020-05-22 22:40 ` [PATCH v8 07/19] mtd: spi-nor: sfdp: prepare BFPT parsing for JESD216 rev D Pratyush Yadav
2020-05-22 22:40 ` Pratyush Yadav
2020-05-22 22:40 ` Pratyush Yadav
2020-05-22 22:40 ` Pratyush Yadav
2020-05-22 22:40 ` [PATCH v8 08/19] mtd: spi-nor: sfdp: get command opcode extension type from BFPT Pratyush Yadav
2020-05-22 22:40 ` Pratyush Yadav
2020-05-22 22:40 ` Pratyush Yadav
2020-05-22 22:40 ` Pratyush Yadav
2020-05-22 22:40 ` [PATCH v8 09/19] mtd: spi-nor: sfdp: parse xSPI Profile 1.0 table Pratyush Yadav
2020-05-22 22:40 ` Pratyush Yadav
2020-05-22 22:40 ` Pratyush Yadav
2020-05-22 22:40 ` Pratyush Yadav
2020-05-22 22:40 ` [PATCH v8 10/19] mtd: spi-nor: core: use dummy cycle and address width info from SFDP Pratyush Yadav
2020-05-22 22:40 ` Pratyush Yadav
2020-05-22 22:40 ` Pratyush Yadav
2020-05-22 22:40 ` Pratyush Yadav
2020-05-22 22:40 ` [PATCH v8 11/19] mtd: spi-nor: core: do 2 byte reads for SR and FSR in DTR mode Pratyush Yadav
2020-05-22 22:40 ` Pratyush Yadav
2020-05-22 22:40 ` Pratyush Yadav
2020-05-22 22:40 ` Pratyush Yadav
2020-05-22 22:40 ` [PATCH v8 12/19] mtd: spi-nor: core: enable octal DTR mode when possible Pratyush Yadav
2020-05-22 22:40 ` Pratyush Yadav
2020-05-22 22:40 ` Pratyush Yadav
2020-05-22 22:40 ` Pratyush Yadav
2020-05-22 22:40 ` [PATCH v8 13/19] mtd: spi-nor: sfdp: do not make invalid quad enable fatal Pratyush Yadav
2020-05-22 22:40 ` Pratyush Yadav
2020-05-22 22:40 ` Pratyush Yadav
2020-05-22 22:40 ` Pratyush Yadav
2020-05-22 22:40 ` [PATCH v8 14/19] mtd: spi-nor: sfdp: detect Soft Reset sequence support from BFPT Pratyush Yadav
2020-05-22 22:40 ` Pratyush Yadav
2020-05-22 22:40 ` Pratyush Yadav
2020-05-22 22:40 ` Pratyush Yadav
2020-05-22 22:40 ` [PATCH v8 15/19] mtd: spi-nor: core: perform a Soft Reset on shutdown Pratyush Yadav
2020-05-22 22:40 ` Pratyush Yadav
2020-05-22 22:40 ` Pratyush Yadav
2020-05-22 22:40 ` Pratyush Yadav
2020-05-22 22:40 ` [PATCH v8 16/19] mtd: spi-nor: core: disable Octal DTR mode on suspend Pratyush Yadav
2020-05-22 22:40 ` Pratyush Yadav
2020-05-22 22:40 ` Pratyush Yadav
2020-05-22 22:40 ` Pratyush Yadav
2020-05-22 22:40 ` [PATCH v8 17/19] mtd: spi-nor: core: expose spi_nor_default_setup() in core.h Pratyush Yadav
2020-05-22 22:40 ` Pratyush Yadav
2020-05-22 22:40 ` Pratyush Yadav
2020-05-22 22:40 ` Pratyush Yadav
2020-05-22 22:40 ` [PATCH v8 18/19] mtd: spi-nor: spansion: add support for Cypress Semper flash Pratyush Yadav
2020-05-22 22:40 ` Pratyush Yadav
2020-05-22 22:40 ` Pratyush Yadav
2020-05-22 22:40 ` Pratyush Yadav
2020-05-22 22:40 ` [PATCH v8 19/19] mtd: spi-nor: micron-st: allow using MT35XU512ABA in Octal DTR mode Pratyush Yadav
2020-05-22 22:40 ` Pratyush Yadav
2020-05-22 22:40 ` Pratyush Yadav
2020-05-22 22:40 ` Pratyush Yadav
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