From: Jim Quinlan <james.quinlan@broadcom.com> To: linux-pci@vger.kernel.org, Christoph Hellwig <hch@lst.de>, Nicolas Saenz Julienne <nsaenzjulienne@suse.de>, bcm-kernel-feedback-list@broadcom.com, james.quinlan@broadcom.com Cc: Jim Quinlan <james.quinlan@broadcom.com>, Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>, Rob Herring <robh@kernel.org>, Bjorn Helgaas <bhelgaas@google.com>, Florian Fainelli <f.fainelli@gmail.com>, linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v4 06/12] PCI: brcmstb: Add bcm7278 PERST support Date: Fri, 5 Jun 2020 17:26:46 -0400 [thread overview] Message-ID: <20200605212706.7361-7-james.quinlan@broadcom.com> (raw) In-Reply-To: <20200605212706.7361-1-james.quinlan@broadcom.com> From: Jim Quinlan <jquinlan@broadcom.com> The PERST bit was moved to a different register in 7278-type STB chips. In addition, the polarity of the bit was also changed; for other chips writing a 1 specified assert; for 7278-type chips, writing a 0 specifies assert. Signal-wise, PERST is an asserted-low signal. Signed-off-by: Jim Quinlan <jquinlan@broadcom.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> --- drivers/pci/controller/pcie-brcmstb.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c index 69d49d675b4a..532ea9c9cf89 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -81,6 +81,7 @@ #define PCIE_MISC_PCIE_CTRL 0x4064 #define PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK 0x1 +#define PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_MASK 0x4 #define PCIE_MISC_PCIE_STATUS 0x4068 #define PCIE_MISC_PCIE_STATUS_PCIE_PORT_MASK 0x80 @@ -686,9 +687,17 @@ static inline void brcm_pcie_perst_set(struct brcm_pcie *pcie, u32 val) { u32 tmp; - tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); - u32p_replace_bits(&tmp, val, PCIE_RGR1_SW_INIT_1_PERST_MASK); - writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); + if (pcie->type == BCM7278) { + /* Perst bit has moved and assert value is 0 */ + tmp = readl(pcie->base + PCIE_MISC_PCIE_CTRL); + u32p_replace_bits(&tmp, + !val, PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_MASK); + writel(tmp, pcie->base + PCIE_MISC_PCIE_CTRL); + } else { + tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); + u32p_replace_bits(&tmp, val, PCIE_RGR1_SW_INIT_1_PERST_MASK); + writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); + } } static inline int brcm_pcie_get_rc_bar2_size_and_offset(struct brcm_pcie *pcie, -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Jim Quinlan <james.quinlan@broadcom.com> To: linux-pci@vger.kernel.org, Christoph Hellwig <hch@lst.de>, Nicolas Saenz Julienne <nsaenzjulienne@suse.de>, bcm-kernel-feedback-list@broadcom.com, james.quinlan@broadcom.com Cc: Rob Herring <robh@kernel.org>, Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>, open list <linux-kernel@vger.kernel.org>, Florian Fainelli <f.fainelli@gmail.com>, "moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE" <linux-rpi-kernel@lists.infradead.org>, Jim Quinlan <james.quinlan@broadcom.com>, Bjorn Helgaas <bhelgaas@google.com>, "moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE" <linux-arm-kernel@lists.infradead.org> Subject: [PATCH v4 06/12] PCI: brcmstb: Add bcm7278 PERST support Date: Fri, 5 Jun 2020 17:26:46 -0400 [thread overview] Message-ID: <20200605212706.7361-7-james.quinlan@broadcom.com> (raw) In-Reply-To: <20200605212706.7361-1-james.quinlan@broadcom.com> From: Jim Quinlan <jquinlan@broadcom.com> The PERST bit was moved to a different register in 7278-type STB chips. In addition, the polarity of the bit was also changed; for other chips writing a 1 specified assert; for 7278-type chips, writing a 0 specifies assert. Signal-wise, PERST is an asserted-low signal. Signed-off-by: Jim Quinlan <jquinlan@broadcom.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> --- drivers/pci/controller/pcie-brcmstb.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c index 69d49d675b4a..532ea9c9cf89 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -81,6 +81,7 @@ #define PCIE_MISC_PCIE_CTRL 0x4064 #define PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK 0x1 +#define PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_MASK 0x4 #define PCIE_MISC_PCIE_STATUS 0x4068 #define PCIE_MISC_PCIE_STATUS_PCIE_PORT_MASK 0x80 @@ -686,9 +687,17 @@ static inline void brcm_pcie_perst_set(struct brcm_pcie *pcie, u32 val) { u32 tmp; - tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); - u32p_replace_bits(&tmp, val, PCIE_RGR1_SW_INIT_1_PERST_MASK); - writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); + if (pcie->type == BCM7278) { + /* Perst bit has moved and assert value is 0 */ + tmp = readl(pcie->base + PCIE_MISC_PCIE_CTRL); + u32p_replace_bits(&tmp, + !val, PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_MASK); + writel(tmp, pcie->base + PCIE_MISC_PCIE_CTRL); + } else { + tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); + u32p_replace_bits(&tmp, val, PCIE_RGR1_SW_INIT_1_PERST_MASK); + writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); + } } static inline int brcm_pcie_get_rc_bar2_size_and_offset(struct brcm_pcie *pcie, -- 2.17.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-06-05 21:27 UTC|newest] Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-06-05 21:26 [PATCH v4 00/12] PCI: brcmstb: enable PCIe for STB chips Jim Quinlan 2020-06-05 21:26 ` Jim Quinlan 2020-06-05 21:26 ` Jim Quinlan 2020-06-05 21:26 ` Jim Quinlan via iommu 2020-06-05 21:26 ` Jim Quinlan 2020-06-05 21:26 ` Jim Quinlan 2020-06-05 21:26 ` [PATCH v4 01/12] PCI: brcmstb: PCIE_BRCMSTB depends on ARCH_BRCMSTB Jim Quinlan 2020-06-05 21:26 ` [PATCH v4 02/12] ata: ahci_brcm: Fix use of BCM7216 reset controller Jim Quinlan 2020-06-05 21:26 ` [PATCH v4 03/12] dt-bindings: PCI: Add bindings for more Brcmstb chips Jim Quinlan 2020-06-05 21:26 ` Jim Quinlan 2020-06-15 17:48 ` Rob Herring 2020-06-15 17:48 ` Rob Herring 2020-06-05 21:26 ` [PATCH v4 04/12] PCI: brcmstb: Add bcm7278 register info Jim Quinlan 2020-06-05 21:26 ` Jim Quinlan 2020-06-05 21:26 ` [PATCH v4 05/12] PCI: brcmstb: Add suspend and resume pm_ops Jim Quinlan 2020-06-05 21:26 ` Jim Quinlan 2020-06-05 21:41 ` Florian Fainelli 2020-06-05 21:41 ` Florian Fainelli 2020-06-05 21:26 ` Jim Quinlan [this message] 2020-06-05 21:26 ` [PATCH v4 06/12] PCI: brcmstb: Add bcm7278 PERST support Jim Quinlan 2020-06-05 21:26 ` [PATCH v4 07/12] PCI: brcmstb: Add control of rescal reset Jim Quinlan 2020-06-05 21:26 ` Jim Quinlan 2020-06-05 21:26 ` [PATCH v4 08/12] device core: Introduce multiple dma pfn offsets Jim Quinlan 2020-06-05 21:26 ` Jim Quinlan 2020-06-05 21:26 ` Jim Quinlan via iommu 2020-06-07 16:49 ` Andy Shevchenko 2020-06-07 16:49 ` Andy Shevchenko 2020-06-07 16:49 ` Andy Shevchenko 2020-06-08 15:48 ` Jim Quinlan 2020-06-08 15:48 ` Jim Quinlan 2020-06-08 15:48 ` Jim Quinlan via iommu 2020-06-09 11:18 ` Andy Shevchenko 2020-06-09 11:18 ` Andy Shevchenko 2020-06-09 11:18 ` Andy Shevchenko 2020-06-09 13:13 ` Jim Quinlan 2020-06-09 13:13 ` Jim Quinlan 2020-06-09 13:13 ` Jim Quinlan via iommu 2020-06-05 21:26 ` [PATCH v4 09/12] PCI: brcmstb: Set internal memory viewport sizes Jim Quinlan 2020-06-05 21:26 ` Jim Quinlan 2020-06-05 21:26 ` [PATCH v4 10/12] PCI: brcmstb: Accommodate MSI for older chips Jim Quinlan 2020-06-05 21:26 ` Jim Quinlan 2020-06-05 21:26 ` [PATCH v4 11/12] PCI: brcmstb: Set bus max burst size by chip type Jim Quinlan 2020-06-05 21:26 ` Jim Quinlan 2020-06-05 21:26 ` [PATCH v4 12/12] PCI: brcmstb: Add bcm7211, bcm7216, bcm7445, bcm7278 to match list Jim Quinlan 2020-06-05 21:26 ` Jim Quinlan
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