From: Hans de Goede <hdegoede@redhat.com>
To: "Thierry Reding" <thierry.reding@gmail.com>,
"Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>,
"Jani Nikula" <jani.nikula@linux.intel.com>,
"Joonas Lahtinen" <joonas.lahtinen@linux.intel.com>,
"Ville Syrjälä" <ville.syrjala@linux.intel.com>,
"Rafael J . Wysocki" <rjw@rjwysocki.net>,
"Len Brown" <lenb@kernel.org>
Cc: Hans de Goede <hdegoede@redhat.com>,
linux-pwm@vger.kernel.org,
intel-gfx <intel-gfx@lists.freedesktop.org>,
dri-devel@lists.freedesktop.org,
Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
Mika Westerberg <mika.westerberg@linux.intel.com>,
linux-acpi@vger.kernel.org
Subject: [PATCH 01/16] ACPI / LPSS: Resume Cherry Trail PWM controller in no-irq phase
Date: Sat, 6 Jun 2020 22:25:46 +0200 [thread overview]
Message-ID: <20200606202601.48410-2-hdegoede@redhat.com> (raw)
In-Reply-To: <20200606202601.48410-1-hdegoede@redhat.com>
The DSDTs on most Cherry Trail devices have an ugly clutch where the PWM
controller gets poked from the _PS0 method of the graphics-card device:
Local0 = PSAT /* \_SB_.PCI0.GFX0.PSAT */
If (((Local0 & 0x03) == 0x03))
{
PSAT &= 0xFFFFFFFC
Local1 = PSAT /* \_SB_.PCI0.GFX0.PSAT */
RSTA = Zero
RSTF = Zero
RSTA = One
RSTF = One
PWMB |= 0xC0000000
PWMC = PWMB /* \_SB_.PCI0.GFX0.PWMB */
}
Where PSAT is the power-status register of the PWM controller, so if it
is in D3 when the GFX0 device's PS0 method runs then it will turn it on
and restore the PWM ctrl register value it saved from its PS3 handler.
Note not only does it restore it, it ors it with 0xC0000000 turning it
on at a time where we may not want it to get turned on at all.
The pwm_get call which the i915 driver does to get a reference to the
PWM controller, already adds a device-link making the GFX0 device a
consumer of the PWM device. So it should already have been resumed when
the above AML runs and the AML should thus not do its undesirable poking
of the PWM controller register.
But the PCI core powers on PCI devices in the no-irq resume phase and
thus calls the troublesome PS0 method in the no-irq resume phase.
Where as LPSS devices by default are resumed in the early resume phase.
This commit sets the resume_from_noirq flag in the bsw_pwm_dev_desc
struct, so that Cherry Trail PWM controllers will be resumed in the
no-irq phase. Together with the device-link added by the pwm-get this
ensures that the PWM controller will be on when the troublesome PS0
method runs, which stops it from poking the PWM controller.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
drivers/acpi/acpi_lpss.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/acpi/acpi_lpss.c b/drivers/acpi/acpi_lpss.c
index 5e2bfbcf526f..67892fc0b822 100644
--- a/drivers/acpi/acpi_lpss.c
+++ b/drivers/acpi/acpi_lpss.c
@@ -257,6 +257,7 @@ static const struct lpss_device_desc bsw_pwm_dev_desc = {
.flags = LPSS_SAVE_CTX | LPSS_NO_D3_DELAY,
.prv_offset = 0x800,
.setup = bsw_pwm_setup,
+ .resume_from_noirq = true,
};
static const struct lpss_device_desc byt_uart_dev_desc = {
--
2.26.2
WARNING: multiple messages have this Message-ID (diff)
From: Hans de Goede <hdegoede@redhat.com>
To: "Thierry Reding" <thierry.reding@gmail.com>,
"Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>,
"Jani Nikula" <jani.nikula@linux.intel.com>,
"Joonas Lahtinen" <joonas.lahtinen@linux.intel.com>,
"Ville Syrjälä" <ville.syrjala@linux.intel.com>,
"Rafael J . Wysocki" <rjw@rjwysocki.net>,
"Len Brown" <lenb@kernel.org>
Cc: linux-pwm@vger.kernel.org, linux-acpi@vger.kernel.org,
intel-gfx <intel-gfx@lists.freedesktop.org>,
dri-devel@lists.freedesktop.org,
Hans de Goede <hdegoede@redhat.com>,
Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
Mika Westerberg <mika.westerberg@linux.intel.com>
Subject: [PATCH 01/16] ACPI / LPSS: Resume Cherry Trail PWM controller in no-irq phase
Date: Sat, 6 Jun 2020 22:25:46 +0200 [thread overview]
Message-ID: <20200606202601.48410-2-hdegoede@redhat.com> (raw)
In-Reply-To: <20200606202601.48410-1-hdegoede@redhat.com>
The DSDTs on most Cherry Trail devices have an ugly clutch where the PWM
controller gets poked from the _PS0 method of the graphics-card device:
Local0 = PSAT /* \_SB_.PCI0.GFX0.PSAT */
If (((Local0 & 0x03) == 0x03))
{
PSAT &= 0xFFFFFFFC
Local1 = PSAT /* \_SB_.PCI0.GFX0.PSAT */
RSTA = Zero
RSTF = Zero
RSTA = One
RSTF = One
PWMB |= 0xC0000000
PWMC = PWMB /* \_SB_.PCI0.GFX0.PWMB */
}
Where PSAT is the power-status register of the PWM controller, so if it
is in D3 when the GFX0 device's PS0 method runs then it will turn it on
and restore the PWM ctrl register value it saved from its PS3 handler.
Note not only does it restore it, it ors it with 0xC0000000 turning it
on at a time where we may not want it to get turned on at all.
The pwm_get call which the i915 driver does to get a reference to the
PWM controller, already adds a device-link making the GFX0 device a
consumer of the PWM device. So it should already have been resumed when
the above AML runs and the AML should thus not do its undesirable poking
of the PWM controller register.
But the PCI core powers on PCI devices in the no-irq resume phase and
thus calls the troublesome PS0 method in the no-irq resume phase.
Where as LPSS devices by default are resumed in the early resume phase.
This commit sets the resume_from_noirq flag in the bsw_pwm_dev_desc
struct, so that Cherry Trail PWM controllers will be resumed in the
no-irq phase. Together with the device-link added by the pwm-get this
ensures that the PWM controller will be on when the troublesome PS0
method runs, which stops it from poking the PWM controller.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
drivers/acpi/acpi_lpss.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/acpi/acpi_lpss.c b/drivers/acpi/acpi_lpss.c
index 5e2bfbcf526f..67892fc0b822 100644
--- a/drivers/acpi/acpi_lpss.c
+++ b/drivers/acpi/acpi_lpss.c
@@ -257,6 +257,7 @@ static const struct lpss_device_desc bsw_pwm_dev_desc = {
.flags = LPSS_SAVE_CTX | LPSS_NO_D3_DELAY,
.prv_offset = 0x800,
.setup = bsw_pwm_setup,
+ .resume_from_noirq = true,
};
static const struct lpss_device_desc byt_uart_dev_desc = {
--
2.26.2
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
WARNING: multiple messages have this Message-ID (diff)
From: Hans de Goede <hdegoede@redhat.com>
To: "Thierry Reding" <thierry.reding@gmail.com>,
"Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>,
"Jani Nikula" <jani.nikula@linux.intel.com>,
"Joonas Lahtinen" <joonas.lahtinen@linux.intel.com>,
"Ville Syrjälä" <ville.syrjala@linux.intel.com>,
"Rafael J . Wysocki" <rjw@rjwysocki.net>,
"Len Brown" <lenb@kernel.org>
Cc: linux-pwm@vger.kernel.org, linux-acpi@vger.kernel.org,
intel-gfx <intel-gfx@lists.freedesktop.org>,
dri-devel@lists.freedesktop.org,
Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
Mika Westerberg <mika.westerberg@linux.intel.com>
Subject: [Intel-gfx] [PATCH 01/16] ACPI / LPSS: Resume Cherry Trail PWM controller in no-irq phase
Date: Sat, 6 Jun 2020 22:25:46 +0200 [thread overview]
Message-ID: <20200606202601.48410-2-hdegoede@redhat.com> (raw)
In-Reply-To: <20200606202601.48410-1-hdegoede@redhat.com>
The DSDTs on most Cherry Trail devices have an ugly clutch where the PWM
controller gets poked from the _PS0 method of the graphics-card device:
Local0 = PSAT /* \_SB_.PCI0.GFX0.PSAT */
If (((Local0 & 0x03) == 0x03))
{
PSAT &= 0xFFFFFFFC
Local1 = PSAT /* \_SB_.PCI0.GFX0.PSAT */
RSTA = Zero
RSTF = Zero
RSTA = One
RSTF = One
PWMB |= 0xC0000000
PWMC = PWMB /* \_SB_.PCI0.GFX0.PWMB */
}
Where PSAT is the power-status register of the PWM controller, so if it
is in D3 when the GFX0 device's PS0 method runs then it will turn it on
and restore the PWM ctrl register value it saved from its PS3 handler.
Note not only does it restore it, it ors it with 0xC0000000 turning it
on at a time where we may not want it to get turned on at all.
The pwm_get call which the i915 driver does to get a reference to the
PWM controller, already adds a device-link making the GFX0 device a
consumer of the PWM device. So it should already have been resumed when
the above AML runs and the AML should thus not do its undesirable poking
of the PWM controller register.
But the PCI core powers on PCI devices in the no-irq resume phase and
thus calls the troublesome PS0 method in the no-irq resume phase.
Where as LPSS devices by default are resumed in the early resume phase.
This commit sets the resume_from_noirq flag in the bsw_pwm_dev_desc
struct, so that Cherry Trail PWM controllers will be resumed in the
no-irq phase. Together with the device-link added by the pwm-get this
ensures that the PWM controller will be on when the troublesome PS0
method runs, which stops it from poking the PWM controller.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
drivers/acpi/acpi_lpss.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/acpi/acpi_lpss.c b/drivers/acpi/acpi_lpss.c
index 5e2bfbcf526f..67892fc0b822 100644
--- a/drivers/acpi/acpi_lpss.c
+++ b/drivers/acpi/acpi_lpss.c
@@ -257,6 +257,7 @@ static const struct lpss_device_desc bsw_pwm_dev_desc = {
.flags = LPSS_SAVE_CTX | LPSS_NO_D3_DELAY,
.prv_offset = 0x800,
.setup = bsw_pwm_setup,
+ .resume_from_noirq = true,
};
static const struct lpss_device_desc byt_uart_dev_desc = {
--
2.26.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2020-06-06 20:26 UTC|newest]
Thread overview: 71+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-06 20:25 pwm/i915: Convert pwm-crc and i915 driver's PWM code to use the atomic PWM API Hans de Goede
2020-06-06 20:25 ` [Intel-gfx] " Hans de Goede
2020-06-06 20:25 ` Hans de Goede
2020-06-06 20:25 ` Hans de Goede [this message]
2020-06-06 20:25 ` [Intel-gfx] [PATCH 01/16] ACPI / LPSS: Resume Cherry Trail PWM controller in no-irq phase Hans de Goede
2020-06-06 20:25 ` Hans de Goede
2020-06-06 20:25 ` [PATCH 02/16] ACPI / LPSS: Save Cherry Trail PWM ctx registers only once (at activation) Hans de Goede
2020-06-06 20:25 ` [Intel-gfx] " Hans de Goede
2020-06-06 20:25 ` Hans de Goede
2020-06-07 17:03 ` Andy Shevchenko
2020-06-07 17:03 ` [Intel-gfx] " Andy Shevchenko
2020-06-07 17:03 ` Andy Shevchenko
2020-06-07 17:03 ` Andy Shevchenko
2020-06-07 18:14 ` Hans de Goede
2020-06-07 18:14 ` [Intel-gfx] " Hans de Goede
2020-06-07 18:14 ` Hans de Goede
2020-06-06 20:25 ` [PATCH 03/16] pwm: lpss: Add range limit check for the base_unit register value Hans de Goede
2020-06-06 20:25 ` [Intel-gfx] " Hans de Goede
2020-06-06 20:25 ` Hans de Goede
2020-06-06 20:25 ` [PATCH 04/16] pwm: lpss: Fix off by one error in base_unit math in pwm_lpss_prepare() Hans de Goede
2020-06-06 20:25 ` [Intel-gfx] " Hans de Goede
2020-06-06 20:25 ` Hans de Goede
2020-06-06 20:25 ` [PATCH 05/16] pwm: lpss: Set SW_UPDATE bit when enabling the PWM Hans de Goede
2020-06-06 20:25 ` [Intel-gfx] " Hans de Goede
2020-06-06 20:25 ` Hans de Goede
2020-06-06 20:25 ` [PATCH 06/16] pwm: lpss: Add debug prints, test patch for moving i915 to atomic PWM Hans de Goede
2020-06-06 20:25 ` [Intel-gfx] " Hans de Goede
2020-06-06 20:25 ` Hans de Goede
2020-06-06 20:25 ` [PATCH 07/16] pwm: crc: Fix period / duty_cycle times being off by a factor of 256 Hans de Goede
2020-06-06 20:25 ` [Intel-gfx] " Hans de Goede
2020-06-06 20:25 ` Hans de Goede
2020-06-06 20:25 ` [PATCH 08/16] pwm: crc: Fix off-by-one error in the clock-divider calculations Hans de Goede
2020-06-06 20:25 ` [Intel-gfx] " Hans de Goede
2020-06-06 20:25 ` Hans de Goede
2020-06-06 20:25 ` [PATCH 09/16] pwm: crc: Fix period changes not having any effect Hans de Goede
2020-06-06 20:25 ` [Intel-gfx] " Hans de Goede
2020-06-06 20:25 ` Hans de Goede
2020-06-06 20:25 ` [PATCH 10/16] pwm: crc: Enable/disable PWM output on enable/disable Hans de Goede
2020-06-06 20:25 ` [Intel-gfx] " Hans de Goede
2020-06-06 20:25 ` Hans de Goede
2020-06-06 20:25 ` [PATCH 11/16] pwm: crc: Implement apply() method to support the new atomic PWM API Hans de Goede
2020-06-06 20:25 ` [Intel-gfx] " Hans de Goede
2020-06-06 20:25 ` Hans de Goede
2020-06-06 20:25 ` [PATCH 12/16] pwm: crc: Implement get_state() method Hans de Goede
2020-06-06 20:25 ` [Intel-gfx] " Hans de Goede
2020-06-06 20:25 ` Hans de Goede
2020-06-06 20:25 ` [PATCH 13/16] drm/i915: panel: Add get_vbt_pwm_freq() helper Hans de Goede
2020-06-06 20:25 ` [Intel-gfx] " Hans de Goede
2020-06-06 20:25 ` Hans de Goede
2020-06-06 20:25 ` [PATCH 14/16] drm/i915: panel: Honor the VBT PWM frequency for devs with an external PWM controller Hans de Goede
2020-06-06 20:25 ` [Intel-gfx] " Hans de Goede
2020-06-06 20:25 ` Hans de Goede
2020-06-06 20:26 ` [PATCH 15/16] drm/i915: panel: Honor the VBT PWM min setting " Hans de Goede
2020-06-06 20:26 ` [Intel-gfx] " Hans de Goede
2020-06-06 20:26 ` Hans de Goede
2020-06-06 20:26 ` [PATCH 16/16] drm/i915: panel: Use atomic PWM API " Hans de Goede
2020-06-06 20:26 ` [Intel-gfx] " Hans de Goede
2020-06-06 20:26 ` Hans de Goede
2020-06-06 20:47 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [01/16] ACPI / LPSS: Resume Cherry Trail PWM controller in no-irq phase Patchwork
2020-06-07 18:15 ` pwm/i915: Convert pwm-crc and i915 driver's PWM code to use the atomic PWM API Hans de Goede
2020-06-07 18:15 ` [Intel-gfx] " Hans de Goede
2020-06-07 18:15 ` Hans de Goede
2020-06-08 14:35 ` Daniel Vetter
2020-06-08 14:35 ` [Intel-gfx] " Daniel Vetter
2020-06-08 14:35 ` Daniel Vetter
2020-06-11 21:21 ` Uwe Kleine-König
2020-06-11 21:21 ` [Intel-gfx] " Uwe Kleine-König
2020-06-11 21:21 ` Uwe Kleine-König
2020-06-12 17:04 ` Hans de Goede
2020-06-12 17:04 ` [Intel-gfx] " Hans de Goede
2020-06-12 17:04 ` Hans de Goede
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200606202601.48410-2-hdegoede@redhat.com \
--to=hdegoede@redhat.com \
--cc=andriy.shevchenko@linux.intel.com \
--cc=dri-devel@lists.freedesktop.org \
--cc=intel-gfx@lists.freedesktop.org \
--cc=jani.nikula@linux.intel.com \
--cc=joonas.lahtinen@linux.intel.com \
--cc=lenb@kernel.org \
--cc=linux-acpi@vger.kernel.org \
--cc=linux-pwm@vger.kernel.org \
--cc=mika.westerberg@linux.intel.com \
--cc=rjw@rjwysocki.net \
--cc=thierry.reding@gmail.com \
--cc=u.kleine-koenig@pengutronix.de \
--cc=ville.syrjala@linux.intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.