From: Keqian Zhu <zhukeqian1@huawei.com>
To: <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<kvmarm@lists.cs.columbia.edu>, <kvm@vger.kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>,
Marc Zyngier <maz@kernel.org>, James Morse <james.morse@arm.com>,
Will Deacon <will@kernel.org>,
"Suzuki K Poulose" <suzuki.poulose@arm.com>,
Sean Christopherson <sean.j.christopherson@intel.com>,
Julien Thierry <julien.thierry.kdev@gmail.com>,
Mark Brown <broonie@kernel.org>,
"Thomas Gleixner" <tglx@linutronix.de>,
Andrew Morton <akpm@linux-foundation.org>,
Alexios Zavras <alexios.zavras@intel.com>,
<liangpeng10@huawei.com>, <zhengxiang9@huawei.com>,
<wanghaibin.wang@huawei.com>, Keqian Zhu <zhukeqian1@huawei.com>
Subject: [PATCH 06/12] KVM: arm64: Set DBM bit of PTEs during write protecting
Date: Tue, 16 Jun 2020 17:35:47 +0800 [thread overview]
Message-ID: <20200616093553.27512-7-zhukeqian1@huawei.com> (raw)
In-Reply-To: <20200616093553.27512-1-zhukeqian1@huawei.com>
During write protecting PTEs, if hardware dirty log is enabled,
set the DBM bit of PTEs when they are *already writable*. This
ensures some mechanisms that rely on "write fault", such as CoW,
are not broken.
Signed-off-by: Keqian Zhu <zhukeqian1@huawei.com>
Signed-off-by: Peng Liang <liangpeng10@huawei.com>
---
arch/arm64/kvm/mmu.c | 15 ++++++++++-----
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/kvm/mmu.c b/arch/arm64/kvm/mmu.c
index f08b0fbca0a0..742c7943176f 100644
--- a/arch/arm64/kvm/mmu.c
+++ b/arch/arm64/kvm/mmu.c
@@ -1536,19 +1536,24 @@ int kvm_phys_addr_ioremap(struct kvm *kvm, phys_addr_t guest_ipa,
/**
* stage2_wp_ptes - write protect PMD range
+ * @kvm: kvm instance for the VM
* @pmd: pointer to pmd entry
* @addr: range start address
* @end: range end address
*/
-static void stage2_wp_ptes(pmd_t *pmd, phys_addr_t addr, phys_addr_t end)
+static void stage2_wp_ptes(struct kvm *kvm, pmd_t *pmd,
+ phys_addr_t addr, phys_addr_t end)
{
pte_t *pte;
pte = pte_offset_kernel(pmd, addr);
do {
- if (!pte_none(*pte)) {
- if (!kvm_s2pte_readonly(pte))
- kvm_set_s2pte_readonly(pte);
+ if (!pte_none(*pte) && !kvm_s2pte_readonly(pte)) {
+#ifdef CONFIG_ARM64_HW_AFDBM
+ if (kvm->arch.hw_dirty_log && !kvm_s2pte_dbm(pte))
+ kvm_set_s2pte_dbm(pte);
+#endif
+ kvm_set_s2pte_readonly(pte);
}
} while (pte++, addr += PAGE_SIZE, addr != end);
}
@@ -1575,7 +1580,7 @@ static void stage2_wp_pmds(struct kvm *kvm, pud_t *pud,
if (!kvm_s2pmd_readonly(pmd))
kvm_set_s2pmd_readonly(pmd);
} else {
- stage2_wp_ptes(pmd, addr, next);
+ stage2_wp_ptes(kvm, pmd, addr, next);
}
}
} while (pmd++, addr = next, addr != end);
--
2.19.1
WARNING: multiple messages have this Message-ID (diff)
From: Keqian Zhu <zhukeqian1@huawei.com>
To: <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<kvmarm@lists.cs.columbia.edu>, <kvm@vger.kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>,
Sean Christopherson <sean.j.christopherson@intel.com>,
liangpeng10@huawei.com, Alexios Zavras <alexios.zavras@intel.com>,
Mark Brown <broonie@kernel.org>, Marc Zyngier <maz@kernel.org>,
Thomas Gleixner <tglx@linutronix.de>,
Will Deacon <will@kernel.org>,
Andrew Morton <akpm@linux-foundation.org>
Subject: [PATCH 06/12] KVM: arm64: Set DBM bit of PTEs during write protecting
Date: Tue, 16 Jun 2020 17:35:47 +0800 [thread overview]
Message-ID: <20200616093553.27512-7-zhukeqian1@huawei.com> (raw)
In-Reply-To: <20200616093553.27512-1-zhukeqian1@huawei.com>
During write protecting PTEs, if hardware dirty log is enabled,
set the DBM bit of PTEs when they are *already writable*. This
ensures some mechanisms that rely on "write fault", such as CoW,
are not broken.
Signed-off-by: Keqian Zhu <zhukeqian1@huawei.com>
Signed-off-by: Peng Liang <liangpeng10@huawei.com>
---
arch/arm64/kvm/mmu.c | 15 ++++++++++-----
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/kvm/mmu.c b/arch/arm64/kvm/mmu.c
index f08b0fbca0a0..742c7943176f 100644
--- a/arch/arm64/kvm/mmu.c
+++ b/arch/arm64/kvm/mmu.c
@@ -1536,19 +1536,24 @@ int kvm_phys_addr_ioremap(struct kvm *kvm, phys_addr_t guest_ipa,
/**
* stage2_wp_ptes - write protect PMD range
+ * @kvm: kvm instance for the VM
* @pmd: pointer to pmd entry
* @addr: range start address
* @end: range end address
*/
-static void stage2_wp_ptes(pmd_t *pmd, phys_addr_t addr, phys_addr_t end)
+static void stage2_wp_ptes(struct kvm *kvm, pmd_t *pmd,
+ phys_addr_t addr, phys_addr_t end)
{
pte_t *pte;
pte = pte_offset_kernel(pmd, addr);
do {
- if (!pte_none(*pte)) {
- if (!kvm_s2pte_readonly(pte))
- kvm_set_s2pte_readonly(pte);
+ if (!pte_none(*pte) && !kvm_s2pte_readonly(pte)) {
+#ifdef CONFIG_ARM64_HW_AFDBM
+ if (kvm->arch.hw_dirty_log && !kvm_s2pte_dbm(pte))
+ kvm_set_s2pte_dbm(pte);
+#endif
+ kvm_set_s2pte_readonly(pte);
}
} while (pte++, addr += PAGE_SIZE, addr != end);
}
@@ -1575,7 +1580,7 @@ static void stage2_wp_pmds(struct kvm *kvm, pud_t *pud,
if (!kvm_s2pmd_readonly(pmd))
kvm_set_s2pmd_readonly(pmd);
} else {
- stage2_wp_ptes(pmd, addr, next);
+ stage2_wp_ptes(kvm, pmd, addr, next);
}
}
} while (pmd++, addr = next, addr != end);
--
2.19.1
_______________________________________________
kvmarm mailing list
kvmarm@lists.cs.columbia.edu
https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
WARNING: multiple messages have this Message-ID (diff)
From: Keqian Zhu <zhukeqian1@huawei.com>
To: <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<kvmarm@lists.cs.columbia.edu>, <kvm@vger.kernel.org>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Keqian Zhu <zhukeqian1@huawei.com>,
Sean Christopherson <sean.j.christopherson@intel.com>,
liangpeng10@huawei.com, Alexios Zavras <alexios.zavras@intel.com>,
zhengxiang9@huawei.com, Mark Brown <broonie@kernel.org>,
James Morse <james.morse@arm.com>, Marc Zyngier <maz@kernel.org>,
wanghaibin.wang@huawei.com, Thomas Gleixner <tglx@linutronix.de>,
Will Deacon <will@kernel.org>,
Andrew Morton <akpm@linux-foundation.org>,
Julien Thierry <julien.thierry.kdev@gmail.com>
Subject: [PATCH 06/12] KVM: arm64: Set DBM bit of PTEs during write protecting
Date: Tue, 16 Jun 2020 17:35:47 +0800 [thread overview]
Message-ID: <20200616093553.27512-7-zhukeqian1@huawei.com> (raw)
In-Reply-To: <20200616093553.27512-1-zhukeqian1@huawei.com>
During write protecting PTEs, if hardware dirty log is enabled,
set the DBM bit of PTEs when they are *already writable*. This
ensures some mechanisms that rely on "write fault", such as CoW,
are not broken.
Signed-off-by: Keqian Zhu <zhukeqian1@huawei.com>
Signed-off-by: Peng Liang <liangpeng10@huawei.com>
---
arch/arm64/kvm/mmu.c | 15 ++++++++++-----
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/kvm/mmu.c b/arch/arm64/kvm/mmu.c
index f08b0fbca0a0..742c7943176f 100644
--- a/arch/arm64/kvm/mmu.c
+++ b/arch/arm64/kvm/mmu.c
@@ -1536,19 +1536,24 @@ int kvm_phys_addr_ioremap(struct kvm *kvm, phys_addr_t guest_ipa,
/**
* stage2_wp_ptes - write protect PMD range
+ * @kvm: kvm instance for the VM
* @pmd: pointer to pmd entry
* @addr: range start address
* @end: range end address
*/
-static void stage2_wp_ptes(pmd_t *pmd, phys_addr_t addr, phys_addr_t end)
+static void stage2_wp_ptes(struct kvm *kvm, pmd_t *pmd,
+ phys_addr_t addr, phys_addr_t end)
{
pte_t *pte;
pte = pte_offset_kernel(pmd, addr);
do {
- if (!pte_none(*pte)) {
- if (!kvm_s2pte_readonly(pte))
- kvm_set_s2pte_readonly(pte);
+ if (!pte_none(*pte) && !kvm_s2pte_readonly(pte)) {
+#ifdef CONFIG_ARM64_HW_AFDBM
+ if (kvm->arch.hw_dirty_log && !kvm_s2pte_dbm(pte))
+ kvm_set_s2pte_dbm(pte);
+#endif
+ kvm_set_s2pte_readonly(pte);
}
} while (pte++, addr += PAGE_SIZE, addr != end);
}
@@ -1575,7 +1580,7 @@ static void stage2_wp_pmds(struct kvm *kvm, pud_t *pud,
if (!kvm_s2pmd_readonly(pmd))
kvm_set_s2pmd_readonly(pmd);
} else {
- stage2_wp_ptes(pmd, addr, next);
+ stage2_wp_ptes(kvm, pmd, addr, next);
}
}
} while (pmd++, addr = next, addr != end);
--
2.19.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-06-16 9:37 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-16 9:35 [PATCH 00/12] KVM: arm64: Support stage2 hardware DBM Keqian Zhu
2020-06-16 9:35 ` Keqian Zhu
2020-06-16 9:35 ` Keqian Zhu
2020-06-16 9:35 ` [PATCH 01/12] KVM: arm64: Add some basic functions to support hw DBM Keqian Zhu
2020-06-16 9:35 ` Keqian Zhu
2020-06-16 9:35 ` Keqian Zhu
2020-06-16 9:35 ` [PATCH 02/12] KVM: arm64: Modify stage2 young mechanism " Keqian Zhu
2020-06-16 9:35 ` Keqian Zhu
2020-06-16 9:35 ` Keqian Zhu
2020-06-16 9:35 ` [PATCH 03/12] KVM: arm64: Report hardware dirty status of stage2 PTE if coverred Keqian Zhu
2020-06-16 9:35 ` Keqian Zhu
2020-06-16 9:35 ` Keqian Zhu
2020-07-01 11:28 ` Steven Price
2020-07-01 11:28 ` Steven Price
2020-07-01 11:28 ` Steven Price
2020-07-02 11:28 ` zhukeqian
2020-07-02 11:28 ` zhukeqian
2020-07-02 11:28 ` zhukeqian
2020-06-16 9:35 ` [PATCH 04/12] KVM: arm64: Support clear DBM bit for PTEs Keqian Zhu
2020-06-16 9:35 ` Keqian Zhu
2020-06-16 9:35 ` Keqian Zhu
2020-06-16 9:35 ` [PATCH 05/12] KVM: arm64: Add KVM_CAP_ARM_HW_DIRTY_LOG capability Keqian Zhu
2020-06-16 9:35 ` Keqian Zhu
2020-06-16 9:35 ` Keqian Zhu
2020-06-16 9:35 ` Keqian Zhu [this message]
2020-06-16 9:35 ` [PATCH 06/12] KVM: arm64: Set DBM bit of PTEs during write protecting Keqian Zhu
2020-06-16 9:35 ` Keqian Zhu
2020-06-16 9:35 ` [PATCH 07/12] KVM: arm64: Scan PTEs to sync dirty log Keqian Zhu
2020-06-16 9:35 ` Keqian Zhu
2020-06-16 9:35 ` Keqian Zhu
2020-06-16 9:35 ` [PATCH 08/12] KVM: Omit dirty log sync in log clear if initially all set Keqian Zhu
2020-06-16 9:35 ` Keqian Zhu
2020-06-16 9:35 ` Keqian Zhu
2020-06-16 9:35 ` [PATCH 09/12] KVM: arm64: Steply write protect page table by mask bit Keqian Zhu
2020-06-16 9:35 ` Keqian Zhu
2020-06-16 9:35 ` Keqian Zhu
2020-06-16 9:35 ` [PATCH 10/12] KVM: arm64: Save stage2 PTE dirty status if it is coverred Keqian Zhu
2020-06-16 9:35 ` Keqian Zhu
2020-06-16 9:35 ` Keqian Zhu
2020-06-16 9:35 ` [PATCH 11/12] KVM: arm64: Support disable hw dirty log after enable Keqian Zhu
2020-06-16 9:35 ` Keqian Zhu
2020-06-16 9:35 ` Keqian Zhu
2020-06-16 9:35 ` [PATCH 12/12] KVM: arm64: Enable stage2 hardware DBM Keqian Zhu
2020-06-16 9:35 ` Keqian Zhu
2020-06-16 9:35 ` Keqian Zhu
2020-06-18 4:13 ` [PATCH 00/12] KVM: arm64: Support " zhukeqian
2020-06-18 4:13 ` zhukeqian
2020-06-18 4:13 ` zhukeqian
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