From: Zhenyu Ye <yezhenyu2@huawei.com>
To: <catalin.marinas@arm.com>, <peterz@infradead.org>,
<mark.rutland@arm.com>, <will@kernel.org>,
<aneesh.kumar@linux.ibm.com>, <akpm@linux-foundation.org>,
<npiggin@gmail.com>, <arnd@arndb.de>, <rostedt@goodmis.org>,
<maz@kernel.org>, <suzuki.poulose@arm.com>, <tglx@linutronix.de>,
<yuzhao@google.com>, <Dave.Martin@arm.com>,
<steven.price@arm.com>, <broonie@kernel.org>,
<guohanjun@huawei.com>
Cc: <yezhenyu2@huawei.com>, <linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <linux-arch@vger.kernel.org>,
<linux-mm@kvack.org>, <arm@kernel.org>, <xiexiangyou@huawei.com>,
<prime.zeng@hisilicon.com>, <zhangshaokun@hisilicon.com>,
<kuhn.chenqun@huawei.com>
Subject: [RESEND PATCH v5 6/6] arm64: tlb: Set the TTL field in flush_*_tlb_range
Date: Thu, 25 Jun 2020 16:03:14 +0800 [thread overview]
Message-ID: <20200625080314.230-7-yezhenyu2@huawei.com> (raw)
In-Reply-To: <20200625080314.230-1-yezhenyu2@huawei.com>
This patch implement flush_{pmd|pud}_tlb_range() in arm64 by
calling __flush_tlb_range() with the corresponding stride and
tlb_level values.
Signed-off-by: Zhenyu Ye <yezhenyu2@huawei.com>
---
arch/arm64/include/asm/pgtable.h | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
index 758e2d1577d0..d5d3fbe73953 100644
--- a/arch/arm64/include/asm/pgtable.h
+++ b/arch/arm64/include/asm/pgtable.h
@@ -40,6 +40,16 @@ extern void __pmd_error(const char *file, int line, unsigned long val);
extern void __pud_error(const char *file, int line, unsigned long val);
extern void __pgd_error(const char *file, int line, unsigned long val);
+#ifdef CONFIG_TRANSPARENT_HUGEPAGE
+#define __HAVE_ARCH_FLUSH_PMD_TLB_RANGE
+
+/* Set stride and tlb_level in flush_*_tlb_range */
+#define flush_pmd_tlb_range(vma, addr, end) \
+ __flush_tlb_range(vma, addr, end, PMD_SIZE, false, 2)
+#define flush_pud_tlb_range(vma, addr, end) \
+ __flush_tlb_range(vma, addr, end, PUD_SIZE, false, 1)
+#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
+
/*
* ZERO_PAGE is a global shared page that is always zero: used
* for zero-mapped memory areas etc..
--
2.26.2
WARNING: multiple messages have this Message-ID (diff)
From: Zhenyu Ye <yezhenyu2@huawei.com>
To: catalin.marinas@arm.com, peterz@infradead.org,
mark.rutland@arm.com, will@kernel.org,
aneesh.kumar@linux.ibm.com, akpm@linux-foundation.org,
npiggin@gmail.com, arnd@arndb.de, rostedt@goodmis.org,
maz@kernel.org, suzuki.poulose@arm.com, tglx@linutronix.de,
yuzhao@google.com, Dave.Martin@arm.com, steven.price@arm.com,
broonie@kernel.org, guohanjun@huawei.com
Cc: yezhenyu2@huawei.com, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org,
linux-mm@kvack.org, arm@kernel.org, xiexiangyou@huawei.com,
prime.zeng@hisilicon.com, zhangshaokun@hisilicon.com,
kuhn.chenqun@huawei.com
Subject: [RESEND PATCH v5 6/6] arm64: tlb: Set the TTL field in flush_*_tlb_range
Date: Thu, 25 Jun 2020 16:03:14 +0800 [thread overview]
Message-ID: <20200625080314.230-7-yezhenyu2@huawei.com> (raw)
In-Reply-To: <20200625080314.230-1-yezhenyu2@huawei.com>
This patch implement flush_{pmd|pud}_tlb_range() in arm64 by
calling __flush_tlb_range() with the corresponding stride and
tlb_level values.
Signed-off-by: Zhenyu Ye <yezhenyu2@huawei.com>
---
arch/arm64/include/asm/pgtable.h | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
index 758e2d1577d0..d5d3fbe73953 100644
--- a/arch/arm64/include/asm/pgtable.h
+++ b/arch/arm64/include/asm/pgtable.h
@@ -40,6 +40,16 @@ extern void __pmd_error(const char *file, int line, unsigned long val);
extern void __pud_error(const char *file, int line, unsigned long val);
extern void __pgd_error(const char *file, int line, unsigned long val);
+#ifdef CONFIG_TRANSPARENT_HUGEPAGE
+#define __HAVE_ARCH_FLUSH_PMD_TLB_RANGE
+
+/* Set stride and tlb_level in flush_*_tlb_range */
+#define flush_pmd_tlb_range(vma, addr, end) \
+ __flush_tlb_range(vma, addr, end, PMD_SIZE, false, 2)
+#define flush_pud_tlb_range(vma, addr, end) \
+ __flush_tlb_range(vma, addr, end, PUD_SIZE, false, 1)
+#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
+
/*
* ZERO_PAGE is a global shared page that is always zero: used
* for zero-mapped memory areas etc..
--
2.26.2
WARNING: multiple messages have this Message-ID (diff)
From: Zhenyu Ye <yezhenyu2@huawei.com>
To: <catalin.marinas@arm.com>, <peterz@infradead.org>,
<mark.rutland@arm.com>, <will@kernel.org>,
<aneesh.kumar@linux.ibm.com>, <akpm@linux-foundation.org>,
<npiggin@gmail.com>, <arnd@arndb.de>, <rostedt@goodmis.org>,
<maz@kernel.org>, <suzuki.poulose@arm.com>, <tglx@linutronix.de>,
<yuzhao@google.com>, <Dave.Martin@arm.com>,
<steven.price@arm.com>, <broonie@kernel.org>,
<guohanjun@huawei.com>
Cc: linux-arch@vger.kernel.org, yezhenyu2@huawei.com,
linux-kernel@vger.kernel.org, xiexiangyou@huawei.com,
zhangshaokun@hisilicon.com, linux-mm@kvack.org, arm@kernel.org,
prime.zeng@hisilicon.com, kuhn.chenqun@huawei.com,
linux-arm-kernel@lists.infradead.org
Subject: [RESEND PATCH v5 6/6] arm64: tlb: Set the TTL field in flush_*_tlb_range
Date: Thu, 25 Jun 2020 16:03:14 +0800 [thread overview]
Message-ID: <20200625080314.230-7-yezhenyu2@huawei.com> (raw)
In-Reply-To: <20200625080314.230-1-yezhenyu2@huawei.com>
This patch implement flush_{pmd|pud}_tlb_range() in arm64 by
calling __flush_tlb_range() with the corresponding stride and
tlb_level values.
Signed-off-by: Zhenyu Ye <yezhenyu2@huawei.com>
---
arch/arm64/include/asm/pgtable.h | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
index 758e2d1577d0..d5d3fbe73953 100644
--- a/arch/arm64/include/asm/pgtable.h
+++ b/arch/arm64/include/asm/pgtable.h
@@ -40,6 +40,16 @@ extern void __pmd_error(const char *file, int line, unsigned long val);
extern void __pud_error(const char *file, int line, unsigned long val);
extern void __pgd_error(const char *file, int line, unsigned long val);
+#ifdef CONFIG_TRANSPARENT_HUGEPAGE
+#define __HAVE_ARCH_FLUSH_PMD_TLB_RANGE
+
+/* Set stride and tlb_level in flush_*_tlb_range */
+#define flush_pmd_tlb_range(vma, addr, end) \
+ __flush_tlb_range(vma, addr, end, PMD_SIZE, false, 2)
+#define flush_pud_tlb_range(vma, addr, end) \
+ __flush_tlb_range(vma, addr, end, PUD_SIZE, false, 1)
+#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
+
/*
* ZERO_PAGE is a global shared page that is always zero: used
* for zero-mapped memory areas etc..
--
2.26.2
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next prev parent reply other threads:[~2020-06-25 8:03 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-25 8:03 [RESEND PATCH v5 0/6] arm64: tlb: add support for TTL feature Zhenyu Ye
2020-06-25 8:03 ` Zhenyu Ye
2020-06-25 8:03 ` Zhenyu Ye
2020-06-25 8:03 ` [RESEND PATCH v5 1/6] arm64: Detect the ARMv8.4 " Zhenyu Ye
2020-06-25 8:03 ` Zhenyu Ye
2020-06-25 8:03 ` Zhenyu Ye
2020-06-25 8:03 ` [RESEND PATCH v5 2/6] arm64: Add level-hinted TLB invalidation helper Zhenyu Ye
2020-06-25 8:03 ` Zhenyu Ye
2020-06-25 8:03 ` Zhenyu Ye
2020-06-25 8:03 ` [RESEND PATCH v5 3/6] arm64: Add tlbi_user_level " Zhenyu Ye
2020-06-25 8:03 ` Zhenyu Ye
2020-06-25 8:03 ` Zhenyu Ye
2020-07-09 16:48 ` Catalin Marinas
2020-07-09 16:48 ` Catalin Marinas
2020-07-10 1:20 ` Zhenyu Ye
2020-07-10 1:20 ` Zhenyu Ye
2020-07-10 1:20 ` Zhenyu Ye
2020-07-10 8:53 ` Catalin Marinas
2020-07-10 8:53 ` Catalin Marinas
2020-06-25 8:03 ` [RESEND PATCH v5 4/6] tlb: mmu_gather: add tlb_flush_*_range APIs Zhenyu Ye
2020-06-25 8:03 ` Zhenyu Ye
2020-06-25 8:03 ` Zhenyu Ye
2020-06-25 8:03 ` [RESEND PATCH v5 5/6] arm64: tlb: Set the TTL field in flush_tlb_range Zhenyu Ye
2020-06-25 8:03 ` Zhenyu Ye
2020-06-25 8:03 ` Zhenyu Ye
2020-06-25 8:03 ` Zhenyu Ye [this message]
2020-06-25 8:03 ` [RESEND PATCH v5 6/6] arm64: tlb: Set the TTL field in flush_*_tlb_range Zhenyu Ye
2020-06-25 8:03 ` Zhenyu Ye
2020-07-07 13:49 ` [RESEND PATCH v5 0/6] arm64: tlb: add support for TTL feature Catalin Marinas
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