From: Alistair Francis <alistair.francis@wdc.com>
To: peter.maydell@linaro.org, qemu-devel@nongnu.org
Cc: alistair23@gmail.com,
Richard Henderson <richard.henderson@linaro.org>,
Alistair Francis <alistair.francis@wdc.com>,
LIU Zhiwei <zhiwei_liu@c-sky.com>
Subject: [PULL 10/63] target/riscv: add fault-only-first unit stride load
Date: Fri, 26 Jun 2020 14:43:17 -0700 [thread overview]
Message-ID: <20200626214410.3613258-11-alistair.francis@wdc.com> (raw)
In-Reply-To: <20200626214410.3613258-1-alistair.francis@wdc.com>
From: LIU Zhiwei <zhiwei_liu@c-sky.com>
The unit-stride fault-only-fault load instructions are used to
vectorize loops with data-dependent exit conditions(while loops).
These instructions execute as a regular load except that they
will only take a trap on element 0.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200623215920.2594-9-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/helper.h | 22 +++++
target/riscv/insn32.decode | 7 ++
target/riscv/insn_trans/trans_rvv.inc.c | 73 ++++++++++++++++
target/riscv/vector_helper.c | 110 ++++++++++++++++++++++++
4 files changed, 212 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index f3650f736e..5c97bc446e 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -224,3 +224,25 @@ DEF_HELPER_6(vsxe_v_b, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vsxe_v_h, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vsxe_v_w, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vsxe_v_d, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_5(vlbff_v_b, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vlbff_v_h, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vlbff_v_w, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vlbff_v_d, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vlhff_v_h, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vlhff_v_w, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vlhff_v_d, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vlwff_v_w, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vlwff_v_d, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vleff_v_b, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vleff_v_h, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vleff_v_w, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vleff_v_d, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vlbuff_v_b, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vlbuff_v_h, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vlbuff_v_w, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vlbuff_v_d, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vlhuff_v_h, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vlhuff_v_w, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vlhuff_v_d, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vlwuff_v_w, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vlwuff_v_d, void, ptr, ptr, tl, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 287d52bcc9..7146aec22a 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -226,6 +226,13 @@ vle_v ... 000 . 00000 ..... 111 ..... 0000111 @r2_nfvm
vlbu_v ... 000 . 00000 ..... 000 ..... 0000111 @r2_nfvm
vlhu_v ... 000 . 00000 ..... 101 ..... 0000111 @r2_nfvm
vlwu_v ... 000 . 00000 ..... 110 ..... 0000111 @r2_nfvm
+vlbff_v ... 100 . 10000 ..... 000 ..... 0000111 @r2_nfvm
+vlhff_v ... 100 . 10000 ..... 101 ..... 0000111 @r2_nfvm
+vlwff_v ... 100 . 10000 ..... 110 ..... 0000111 @r2_nfvm
+vleff_v ... 000 . 10000 ..... 111 ..... 0000111 @r2_nfvm
+vlbuff_v ... 000 . 10000 ..... 000 ..... 0000111 @r2_nfvm
+vlhuff_v ... 000 . 10000 ..... 101 ..... 0000111 @r2_nfvm
+vlwuff_v ... 000 . 10000 ..... 110 ..... 0000111 @r2_nfvm
vsb_v ... 000 . 00000 ..... 000 ..... 0100111 @r2_nfvm
vsh_v ... 000 . 00000 ..... 101 ..... 0100111 @r2_nfvm
vsw_v ... 000 . 00000 ..... 110 ..... 0100111 @r2_nfvm
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 11a3a89d54..5e2fbb7078 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -561,3 +561,76 @@ GEN_VEXT_TRANS(vsxb_v, 0, rnfvm, st_index_op, st_index_check)
GEN_VEXT_TRANS(vsxh_v, 1, rnfvm, st_index_op, st_index_check)
GEN_VEXT_TRANS(vsxw_v, 2, rnfvm, st_index_op, st_index_check)
GEN_VEXT_TRANS(vsxe_v, 3, rnfvm, st_index_op, st_index_check)
+
+/*
+ *** unit stride fault-only-first load
+ */
+static bool ldff_trans(uint32_t vd, uint32_t rs1, uint32_t data,
+ gen_helper_ldst_us *fn, DisasContext *s)
+{
+ TCGv_ptr dest, mask;
+ TCGv base;
+ TCGv_i32 desc;
+
+ TCGLabel *over = gen_new_label();
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+
+ dest = tcg_temp_new_ptr();
+ mask = tcg_temp_new_ptr();
+ base = tcg_temp_new();
+ desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
+
+ gen_get_gpr(base, rs1);
+ tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
+ tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
+
+ fn(dest, mask, base, cpu_env, desc);
+
+ tcg_temp_free_ptr(dest);
+ tcg_temp_free_ptr(mask);
+ tcg_temp_free(base);
+ tcg_temp_free_i32(desc);
+ gen_set_label(over);
+ return true;
+}
+
+static bool ldff_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
+{
+ uint32_t data = 0;
+ gen_helper_ldst_us *fn;
+ static gen_helper_ldst_us * const fns[7][4] = {
+ { gen_helper_vlbff_v_b, gen_helper_vlbff_v_h,
+ gen_helper_vlbff_v_w, gen_helper_vlbff_v_d },
+ { NULL, gen_helper_vlhff_v_h,
+ gen_helper_vlhff_v_w, gen_helper_vlhff_v_d },
+ { NULL, NULL,
+ gen_helper_vlwff_v_w, gen_helper_vlwff_v_d },
+ { gen_helper_vleff_v_b, gen_helper_vleff_v_h,
+ gen_helper_vleff_v_w, gen_helper_vleff_v_d },
+ { gen_helper_vlbuff_v_b, gen_helper_vlbuff_v_h,
+ gen_helper_vlbuff_v_w, gen_helper_vlbuff_v_d },
+ { NULL, gen_helper_vlhuff_v_h,
+ gen_helper_vlhuff_v_w, gen_helper_vlhuff_v_d },
+ { NULL, NULL,
+ gen_helper_vlwuff_v_w, gen_helper_vlwuff_v_d }
+ };
+
+ fn = fns[seq][s->sew];
+ if (fn == NULL) {
+ return false;
+ }
+
+ data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
+ data = FIELD_DP32(data, VDATA, VM, a->vm);
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, NF, a->nf);
+ return ldff_trans(a->rd, a->rs1, data, fn, s);
+}
+
+GEN_VEXT_TRANS(vlbff_v, 0, r2nfvm, ldff_op, ld_us_check)
+GEN_VEXT_TRANS(vlhff_v, 1, r2nfvm, ldff_op, ld_us_check)
+GEN_VEXT_TRANS(vlwff_v, 2, r2nfvm, ldff_op, ld_us_check)
+GEN_VEXT_TRANS(vleff_v, 3, r2nfvm, ldff_op, ld_us_check)
+GEN_VEXT_TRANS(vlbuff_v, 4, r2nfvm, ldff_op, ld_us_check)
+GEN_VEXT_TRANS(vlhuff_v, 5, r2nfvm, ldff_op, ld_us_check)
+GEN_VEXT_TRANS(vlwuff_v, 6, r2nfvm, ldff_op, ld_us_check)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 9355958d3f..d4d34d2471 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -577,3 +577,113 @@ GEN_VEXT_ST_INDEX(vsxe_v_b, int8_t, int8_t, idx_b, ste_b)
GEN_VEXT_ST_INDEX(vsxe_v_h, int16_t, int16_t, idx_h, ste_h)
GEN_VEXT_ST_INDEX(vsxe_v_w, int32_t, int32_t, idx_w, ste_w)
GEN_VEXT_ST_INDEX(vsxe_v_d, int64_t, int64_t, idx_d, ste_d)
+
+/*
+ *** unit-stride fault-only-fisrt load instructions
+ */
+static inline void
+vext_ldff(void *vd, void *v0, target_ulong base,
+ CPURISCVState *env, uint32_t desc,
+ vext_ldst_elem_fn *ldst_elem,
+ clear_fn *clear_elem,
+ uint32_t esz, uint32_t msz, uintptr_t ra)
+{
+ void *host;
+ uint32_t i, k, vl = 0;
+ uint32_t mlen = vext_mlen(desc);
+ uint32_t nf = vext_nf(desc);
+ uint32_t vm = vext_vm(desc);
+ uint32_t vlmax = vext_maxsz(desc) / esz;
+ target_ulong addr, offset, remain;
+
+ /* probe every access*/
+ for (i = 0; i < env->vl; i++) {
+ if (!vm && !vext_elem_mask(v0, mlen, i)) {
+ continue;
+ }
+ addr = base + nf * i * msz;
+ if (i == 0) {
+ probe_pages(env, addr, nf * msz, ra, MMU_DATA_LOAD);
+ } else {
+ /* if it triggers an exception, no need to check watchpoint */
+ remain = nf * msz;
+ while (remain > 0) {
+ offset = -(addr | TARGET_PAGE_MASK);
+ host = tlb_vaddr_to_host(env, addr, MMU_DATA_LOAD,
+ cpu_mmu_index(env, false));
+ if (host) {
+#ifdef CONFIG_USER_ONLY
+ if (page_check_range(addr, nf * msz, PAGE_READ) < 0) {
+ vl = i;
+ goto ProbeSuccess;
+ }
+#else
+ probe_pages(env, addr, nf * msz, ra, MMU_DATA_LOAD);
+#endif
+ } else {
+ vl = i;
+ goto ProbeSuccess;
+ }
+ if (remain <= offset) {
+ break;
+ }
+ remain -= offset;
+ addr += offset;
+ }
+ }
+ }
+ProbeSuccess:
+ /* load bytes from guest memory */
+ if (vl != 0) {
+ env->vl = vl;
+ }
+ for (i = 0; i < env->vl; i++) {
+ k = 0;
+ if (!vm && !vext_elem_mask(v0, mlen, i)) {
+ continue;
+ }
+ while (k < nf) {
+ target_ulong addr = base + (i * nf + k) * msz;
+ ldst_elem(env, addr, i + k * vlmax, vd, ra);
+ k++;
+ }
+ }
+ /* clear tail elements */
+ if (vl != 0) {
+ return;
+ }
+ for (k = 0; k < nf; k++) {
+ clear_elem(vd, env->vl + k * vlmax, env->vl * esz, vlmax * esz);
+ }
+}
+
+#define GEN_VEXT_LDFF(NAME, MTYPE, ETYPE, LOAD_FN, CLEAR_FN) \
+void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
+ CPURISCVState *env, uint32_t desc) \
+{ \
+ vext_ldff(vd, v0, base, env, desc, LOAD_FN, CLEAR_FN, \
+ sizeof(ETYPE), sizeof(MTYPE), GETPC()); \
+}
+
+GEN_VEXT_LDFF(vlbff_v_b, int8_t, int8_t, ldb_b, clearb)
+GEN_VEXT_LDFF(vlbff_v_h, int8_t, int16_t, ldb_h, clearh)
+GEN_VEXT_LDFF(vlbff_v_w, int8_t, int32_t, ldb_w, clearl)
+GEN_VEXT_LDFF(vlbff_v_d, int8_t, int64_t, ldb_d, clearq)
+GEN_VEXT_LDFF(vlhff_v_h, int16_t, int16_t, ldh_h, clearh)
+GEN_VEXT_LDFF(vlhff_v_w, int16_t, int32_t, ldh_w, clearl)
+GEN_VEXT_LDFF(vlhff_v_d, int16_t, int64_t, ldh_d, clearq)
+GEN_VEXT_LDFF(vlwff_v_w, int32_t, int32_t, ldw_w, clearl)
+GEN_VEXT_LDFF(vlwff_v_d, int32_t, int64_t, ldw_d, clearq)
+GEN_VEXT_LDFF(vleff_v_b, int8_t, int8_t, lde_b, clearb)
+GEN_VEXT_LDFF(vleff_v_h, int16_t, int16_t, lde_h, clearh)
+GEN_VEXT_LDFF(vleff_v_w, int32_t, int32_t, lde_w, clearl)
+GEN_VEXT_LDFF(vleff_v_d, int64_t, int64_t, lde_d, clearq)
+GEN_VEXT_LDFF(vlbuff_v_b, uint8_t, uint8_t, ldbu_b, clearb)
+GEN_VEXT_LDFF(vlbuff_v_h, uint8_t, uint16_t, ldbu_h, clearh)
+GEN_VEXT_LDFF(vlbuff_v_w, uint8_t, uint32_t, ldbu_w, clearl)
+GEN_VEXT_LDFF(vlbuff_v_d, uint8_t, uint64_t, ldbu_d, clearq)
+GEN_VEXT_LDFF(vlhuff_v_h, uint16_t, uint16_t, ldhu_h, clearh)
+GEN_VEXT_LDFF(vlhuff_v_w, uint16_t, uint32_t, ldhu_w, clearl)
+GEN_VEXT_LDFF(vlhuff_v_d, uint16_t, uint64_t, ldhu_d, clearq)
+GEN_VEXT_LDFF(vlwuff_v_w, uint32_t, uint32_t, ldwu_w, clearl)
+GEN_VEXT_LDFF(vlwuff_v_d, uint32_t, uint64_t, ldwu_d, clearq)
--
2.27.0
next prev parent reply other threads:[~2020-06-26 22:11 UTC|newest]
Thread overview: 77+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-26 21:43 [PULL 00/63] riscv-to-apply queue Alistair Francis
2020-06-26 21:43 ` [PULL 01/63] riscv: plic: Honour source priorities Alistair Francis
2020-06-26 21:43 ` [PULL 02/63] riscv: plic: Add a couple of mising sifive_plic_update calls Alistair Francis
2020-06-26 22:01 ` Jessica Clarke
2020-06-26 21:58 ` Alistair Francis
2020-06-26 21:43 ` [PULL 03/63] target/riscv: add vector extension field in CPURISCVState Alistair Francis
2020-06-26 21:43 ` [PULL 04/63] target/riscv: implementation-defined constant parameters Alistair Francis
2020-06-26 21:43 ` [PULL 05/63] target/riscv: support vector extension csr Alistair Francis
2020-06-26 21:43 ` [PULL 06/63] target/riscv: add vector configure instruction Alistair Francis
2020-06-26 21:43 ` [PULL 07/63] target/riscv: add an internals.h header Alistair Francis
2020-06-26 21:43 ` [PULL 08/63] target/riscv: add vector stride load and store instructions Alistair Francis
2020-06-26 21:43 ` [PULL 09/63] target/riscv: add vector index " Alistair Francis
2020-06-26 21:43 ` Alistair Francis [this message]
2020-06-26 21:43 ` [PULL 11/63] target/riscv: add vector amo operations Alistair Francis
2020-06-26 21:43 ` [PULL 12/63] target/riscv: vector single-width integer add and subtract Alistair Francis
2020-06-26 21:43 ` [PULL 13/63] target/riscv: vector widening " Alistair Francis
2020-06-26 21:43 ` [PULL 14/63] target/riscv: vector integer add-with-carry / subtract-with-borrow instructions Alistair Francis
2020-06-26 21:43 ` [PULL 15/63] target/riscv: vector bitwise logical instructions Alistair Francis
2020-06-26 21:43 ` [PULL 16/63] target/riscv: vector single-width bit shift instructions Alistair Francis
2020-06-26 21:43 ` [PULL 17/63] target/riscv: vector narrowing integer right " Alistair Francis
2020-06-26 21:43 ` [PULL 18/63] target/riscv: vector integer comparison instructions Alistair Francis
2020-06-26 21:43 ` [PULL 19/63] target/riscv: vector integer min/max instructions Alistair Francis
2020-06-26 21:43 ` [PULL 20/63] target/riscv: vector single-width integer multiply instructions Alistair Francis
2020-06-26 21:43 ` [PULL 21/63] target/riscv: vector integer divide instructions Alistair Francis
2020-06-26 21:43 ` [PULL 22/63] target/riscv: vector widening integer multiply instructions Alistair Francis
2020-06-26 21:43 ` [PULL 23/63] target/riscv: vector single-width integer multiply-add instructions Alistair Francis
2020-06-26 21:43 ` [PULL 24/63] target/riscv: vector widening " Alistair Francis
2020-06-26 21:43 ` [PULL 25/63] target/riscv: vector integer merge and move instructions Alistair Francis
2020-06-26 21:43 ` [PULL 26/63] target/riscv: vector single-width saturating add and subtract Alistair Francis
2020-06-26 21:43 ` [PULL 27/63] target/riscv: vector single-width averaging " Alistair Francis
2020-06-26 21:43 ` [PULL 28/63] target/riscv: vector single-width fractional multiply with rounding and saturation Alistair Francis
2020-06-26 21:43 ` [PULL 29/63] target/riscv: vector widening saturating scaled multiply-add Alistair Francis
2020-06-26 21:43 ` [PULL 30/63] target/riscv: vector single-width scaling shift instructions Alistair Francis
2020-06-26 21:43 ` [PULL 31/63] target/riscv: vector narrowing fixed-point clip instructions Alistair Francis
2020-06-26 21:43 ` [PULL 32/63] target/riscv: vector single-width floating-point add/subtract instructions Alistair Francis
2020-06-26 21:43 ` [PULL 33/63] target/riscv: vector widening " Alistair Francis
2020-06-26 21:43 ` [PULL 34/63] target/riscv: vector single-width floating-point multiply/divide instructions Alistair Francis
2020-06-26 21:43 ` [PULL 35/63] target/riscv: vector widening floating-point multiply Alistair Francis
2020-06-26 21:43 ` [PULL 36/63] target/riscv: vector single-width floating-point fused multiply-add instructions Alistair Francis
2020-06-26 21:43 ` [PULL 37/63] target/riscv: vector widening " Alistair Francis
2020-06-26 21:43 ` [PULL 38/63] target/riscv: vector floating-point square-root instruction Alistair Francis
2020-06-26 21:43 ` [PULL 39/63] target/riscv: vector floating-point min/max instructions Alistair Francis
2020-06-26 21:43 ` [PULL 40/63] target/riscv: vector floating-point sign-injection instructions Alistair Francis
2020-06-26 21:43 ` [PULL 41/63] target/riscv: vector floating-point compare instructions Alistair Francis
2020-06-26 21:43 ` [PULL 42/63] target/riscv: vector floating-point classify instructions Alistair Francis
2020-06-26 21:43 ` [PULL 43/63] target/riscv: vector floating-point merge instructions Alistair Francis
2020-06-26 21:43 ` [PULL 44/63] target/riscv: vector floating-point/integer type-convert instructions Alistair Francis
2020-06-26 21:43 ` [PULL 45/63] target/riscv: widening " Alistair Francis
2020-06-26 21:43 ` [PULL 46/63] target/riscv: narrowing " Alistair Francis
2020-06-26 21:43 ` [PULL 47/63] target/riscv: vector single-width integer reduction instructions Alistair Francis
2020-06-26 21:43 ` [PULL 48/63] target/riscv: vector wideing " Alistair Francis
2020-06-26 21:43 ` [PULL 49/63] target/riscv: vector single-width floating-point " Alistair Francis
2020-06-26 21:43 ` [PULL 50/63] target/riscv: vector widening " Alistair Francis
2020-06-26 21:43 ` [PULL 51/63] target/riscv: vector mask-register logical instructions Alistair Francis
2020-06-26 21:43 ` [PULL 52/63] target/riscv: vector mask population count vmpopc Alistair Francis
2020-06-26 21:44 ` [PULL 53/63] target/riscv: vmfirst find-first-set mask bit Alistair Francis
2020-06-26 21:44 ` [PULL 54/63] target/riscv: set-X-first " Alistair Francis
2020-06-26 21:44 ` [PULL 55/63] target/riscv: vector iota instruction Alistair Francis
2020-06-26 21:44 ` [PULL 56/63] target/riscv: vector element index instruction Alistair Francis
2020-06-26 21:44 ` [PULL 57/63] target/riscv: integer extract instruction Alistair Francis
2020-06-26 21:44 ` [PULL 58/63] target/riscv: integer scalar move instruction Alistair Francis
2020-06-26 21:44 ` [PULL 59/63] target/riscv: floating-point scalar move instructions Alistair Francis
2020-06-26 21:44 ` [PULL 60/63] target/riscv: vector slide instructions Alistair Francis
2020-06-26 21:44 ` [PULL 61/63] target/riscv: vector register gather instruction Alistair Francis
2020-06-26 21:44 ` [PULL 62/63] target/riscv: vector compress instruction Alistair Francis
2020-06-26 21:44 ` [PULL 63/63] target/riscv: configure and turn on vector extension from command line Alistair Francis
2020-06-26 22:38 ` [PULL 00/63] riscv-to-apply queue no-reply
2020-06-26 22:44 ` no-reply
2020-06-28 14:30 ` Peter Maydell
2020-06-28 22:51 ` Alistair Francis
2020-06-29 0:52 ` LIU Zhiwei
2020-06-30 6:56 ` LIU Zhiwei
2020-06-30 8:11 ` Thomas Huth
2020-06-30 8:44 ` LIU Zhiwei
2020-08-03 17:53 ` Thomas Huth
2020-08-03 18:00 ` Philippe Mathieu-Daudé
2020-08-03 18:11 ` Thomas Huth
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