From: Alistair Francis <alistair.francis@wdc.com>
To: peter.maydell@linaro.org, qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Alistair Francis <alistair.francis@wdc.com>,
Jessica Clarke <jrtc27@jrtc27.com>
Subject: [PULL 02/63] riscv: plic: Add a couple of mising sifive_plic_update calls
Date: Fri, 26 Jun 2020 14:43:09 -0700 [thread overview]
Message-ID: <20200626214410.3613258-3-alistair.francis@wdc.com> (raw)
In-Reply-To: <20200626214410.3613258-1-alistair.francis@wdc.com>
From: Jessica Clarke <jrtc27@jrtc27.com>
Claiming an interrupt and changing the source priority both potentially
affect whether an interrupt is pending, thus we must re-compute xEIP.
Note that we don't put the sifive_plic_update inside sifive_plic_claim
so that the logging of a claim (and the resulting IRQ) happens before
the state update, making the causal effect clear, and that we drop the
explicit call to sifive_plic_print_state when claiming since
sifive_plic_update already does that automatically at the end for us.
This can result in both spurious interrupt storms if you fail to
complete an IRQ before enabling interrupts (and no other actions occur
that result in a call to sifive_plic_update), but also more importantly
lost interrupts if a disabled interrupt is pending and then becomes
enabled.
Signed-off-by: Jessica Clarke <jrtc27@jrtc27.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20200618210649.22451-1-jrtc27@jrtc27.com
Message-Id: <20200618210649.22451-1-jrtc27@jrtc27.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/sifive_plic.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c
index d91e82b8ab..c20c192034 100644
--- a/hw/riscv/sifive_plic.c
+++ b/hw/riscv/sifive_plic.c
@@ -255,8 +255,8 @@ static uint64_t sifive_plic_read(void *opaque, hwaddr addr, unsigned size)
plic->addr_config[addrid].hartid,
mode_to_char(plic->addr_config[addrid].mode),
value);
- sifive_plic_print_state(plic);
}
+ sifive_plic_update(plic);
return value;
}
}
@@ -287,6 +287,7 @@ static void sifive_plic_write(void *opaque, hwaddr addr, uint64_t value,
qemu_log("plic: write priority: irq=%d priority=%d\n",
irq, plic->source_priority[irq]);
}
+ sifive_plic_update(plic);
return;
} else if (addr >= plic->pending_base && /* 1 bit per source */
addr < plic->pending_base + (plic->num_sources >> 3))
--
2.27.0
next prev parent reply other threads:[~2020-06-26 21:57 UTC|newest]
Thread overview: 77+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-26 21:43 [PULL 00/63] riscv-to-apply queue Alistair Francis
2020-06-26 21:43 ` [PULL 01/63] riscv: plic: Honour source priorities Alistair Francis
2020-06-26 21:43 ` Alistair Francis [this message]
2020-06-26 22:01 ` [PULL 02/63] riscv: plic: Add a couple of mising sifive_plic_update calls Jessica Clarke
2020-06-26 21:58 ` Alistair Francis
2020-06-26 21:43 ` [PULL 03/63] target/riscv: add vector extension field in CPURISCVState Alistair Francis
2020-06-26 21:43 ` [PULL 04/63] target/riscv: implementation-defined constant parameters Alistair Francis
2020-06-26 21:43 ` [PULL 05/63] target/riscv: support vector extension csr Alistair Francis
2020-06-26 21:43 ` [PULL 06/63] target/riscv: add vector configure instruction Alistair Francis
2020-06-26 21:43 ` [PULL 07/63] target/riscv: add an internals.h header Alistair Francis
2020-06-26 21:43 ` [PULL 08/63] target/riscv: add vector stride load and store instructions Alistair Francis
2020-06-26 21:43 ` [PULL 09/63] target/riscv: add vector index " Alistair Francis
2020-06-26 21:43 ` [PULL 10/63] target/riscv: add fault-only-first unit stride load Alistair Francis
2020-06-26 21:43 ` [PULL 11/63] target/riscv: add vector amo operations Alistair Francis
2020-06-26 21:43 ` [PULL 12/63] target/riscv: vector single-width integer add and subtract Alistair Francis
2020-06-26 21:43 ` [PULL 13/63] target/riscv: vector widening " Alistair Francis
2020-06-26 21:43 ` [PULL 14/63] target/riscv: vector integer add-with-carry / subtract-with-borrow instructions Alistair Francis
2020-06-26 21:43 ` [PULL 15/63] target/riscv: vector bitwise logical instructions Alistair Francis
2020-06-26 21:43 ` [PULL 16/63] target/riscv: vector single-width bit shift instructions Alistair Francis
2020-06-26 21:43 ` [PULL 17/63] target/riscv: vector narrowing integer right " Alistair Francis
2020-06-26 21:43 ` [PULL 18/63] target/riscv: vector integer comparison instructions Alistair Francis
2020-06-26 21:43 ` [PULL 19/63] target/riscv: vector integer min/max instructions Alistair Francis
2020-06-26 21:43 ` [PULL 20/63] target/riscv: vector single-width integer multiply instructions Alistair Francis
2020-06-26 21:43 ` [PULL 21/63] target/riscv: vector integer divide instructions Alistair Francis
2020-06-26 21:43 ` [PULL 22/63] target/riscv: vector widening integer multiply instructions Alistair Francis
2020-06-26 21:43 ` [PULL 23/63] target/riscv: vector single-width integer multiply-add instructions Alistair Francis
2020-06-26 21:43 ` [PULL 24/63] target/riscv: vector widening " Alistair Francis
2020-06-26 21:43 ` [PULL 25/63] target/riscv: vector integer merge and move instructions Alistair Francis
2020-06-26 21:43 ` [PULL 26/63] target/riscv: vector single-width saturating add and subtract Alistair Francis
2020-06-26 21:43 ` [PULL 27/63] target/riscv: vector single-width averaging " Alistair Francis
2020-06-26 21:43 ` [PULL 28/63] target/riscv: vector single-width fractional multiply with rounding and saturation Alistair Francis
2020-06-26 21:43 ` [PULL 29/63] target/riscv: vector widening saturating scaled multiply-add Alistair Francis
2020-06-26 21:43 ` [PULL 30/63] target/riscv: vector single-width scaling shift instructions Alistair Francis
2020-06-26 21:43 ` [PULL 31/63] target/riscv: vector narrowing fixed-point clip instructions Alistair Francis
2020-06-26 21:43 ` [PULL 32/63] target/riscv: vector single-width floating-point add/subtract instructions Alistair Francis
2020-06-26 21:43 ` [PULL 33/63] target/riscv: vector widening " Alistair Francis
2020-06-26 21:43 ` [PULL 34/63] target/riscv: vector single-width floating-point multiply/divide instructions Alistair Francis
2020-06-26 21:43 ` [PULL 35/63] target/riscv: vector widening floating-point multiply Alistair Francis
2020-06-26 21:43 ` [PULL 36/63] target/riscv: vector single-width floating-point fused multiply-add instructions Alistair Francis
2020-06-26 21:43 ` [PULL 37/63] target/riscv: vector widening " Alistair Francis
2020-06-26 21:43 ` [PULL 38/63] target/riscv: vector floating-point square-root instruction Alistair Francis
2020-06-26 21:43 ` [PULL 39/63] target/riscv: vector floating-point min/max instructions Alistair Francis
2020-06-26 21:43 ` [PULL 40/63] target/riscv: vector floating-point sign-injection instructions Alistair Francis
2020-06-26 21:43 ` [PULL 41/63] target/riscv: vector floating-point compare instructions Alistair Francis
2020-06-26 21:43 ` [PULL 42/63] target/riscv: vector floating-point classify instructions Alistair Francis
2020-06-26 21:43 ` [PULL 43/63] target/riscv: vector floating-point merge instructions Alistair Francis
2020-06-26 21:43 ` [PULL 44/63] target/riscv: vector floating-point/integer type-convert instructions Alistair Francis
2020-06-26 21:43 ` [PULL 45/63] target/riscv: widening " Alistair Francis
2020-06-26 21:43 ` [PULL 46/63] target/riscv: narrowing " Alistair Francis
2020-06-26 21:43 ` [PULL 47/63] target/riscv: vector single-width integer reduction instructions Alistair Francis
2020-06-26 21:43 ` [PULL 48/63] target/riscv: vector wideing " Alistair Francis
2020-06-26 21:43 ` [PULL 49/63] target/riscv: vector single-width floating-point " Alistair Francis
2020-06-26 21:43 ` [PULL 50/63] target/riscv: vector widening " Alistair Francis
2020-06-26 21:43 ` [PULL 51/63] target/riscv: vector mask-register logical instructions Alistair Francis
2020-06-26 21:43 ` [PULL 52/63] target/riscv: vector mask population count vmpopc Alistair Francis
2020-06-26 21:44 ` [PULL 53/63] target/riscv: vmfirst find-first-set mask bit Alistair Francis
2020-06-26 21:44 ` [PULL 54/63] target/riscv: set-X-first " Alistair Francis
2020-06-26 21:44 ` [PULL 55/63] target/riscv: vector iota instruction Alistair Francis
2020-06-26 21:44 ` [PULL 56/63] target/riscv: vector element index instruction Alistair Francis
2020-06-26 21:44 ` [PULL 57/63] target/riscv: integer extract instruction Alistair Francis
2020-06-26 21:44 ` [PULL 58/63] target/riscv: integer scalar move instruction Alistair Francis
2020-06-26 21:44 ` [PULL 59/63] target/riscv: floating-point scalar move instructions Alistair Francis
2020-06-26 21:44 ` [PULL 60/63] target/riscv: vector slide instructions Alistair Francis
2020-06-26 21:44 ` [PULL 61/63] target/riscv: vector register gather instruction Alistair Francis
2020-06-26 21:44 ` [PULL 62/63] target/riscv: vector compress instruction Alistair Francis
2020-06-26 21:44 ` [PULL 63/63] target/riscv: configure and turn on vector extension from command line Alistair Francis
2020-06-26 22:38 ` [PULL 00/63] riscv-to-apply queue no-reply
2020-06-26 22:44 ` no-reply
2020-06-28 14:30 ` Peter Maydell
2020-06-28 22:51 ` Alistair Francis
2020-06-29 0:52 ` LIU Zhiwei
2020-06-30 6:56 ` LIU Zhiwei
2020-06-30 8:11 ` Thomas Huth
2020-06-30 8:44 ` LIU Zhiwei
2020-08-03 17:53 ` Thomas Huth
2020-08-03 18:00 ` Philippe Mathieu-Daudé
2020-08-03 18:11 ` Thomas Huth
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