From: Catalin Marinas <catalin.marinas@arm.com> To: linux-arm-kernel@lists.infradead.org Cc: linux-mm@kvack.org, linux-arch@vger.kernel.org, Will Deacon <will@kernel.org>, Dave P Martin <Dave.Martin@arm.com>, Vincenzo Frascino <vincenzo.frascino@arm.com>, Szabolcs Nagy <szabolcs.nagy@arm.com>, Kevin Brodsky <kevin.brodsky@arm.com>, Andrey Konovalov <andreyknvl@google.com>, Peter Collingbourne <pcc@google.com>, Andrew Morton <akpm@linux-foundation.org> Subject: [PATCH v6 18/26] arm64: mte: Allow user control of the generated random tags via prctl() Date: Fri, 3 Jul 2020 16:37:10 +0100 [thread overview] Message-ID: <20200703153718.16973-19-catalin.marinas@arm.com> (raw) In-Reply-To: <20200703153718.16973-1-catalin.marinas@arm.com> The IRG, ADDG and SUBG instructions insert a random tag in the resulting address. Certain tags can be excluded via the GCR_EL1.Exclude bitmap when, for example, the user wants a certain colour for freed buffers. Since the GCR_EL1 register is not accessible at EL0, extend the prctl(PR_SET_TAGGED_ADDR_CTRL) interface to include a 16-bit field in the first argument for controlling which tags can be generated by the above instruction (an include rather than exclude mask). Note that by default all non-zero tags are excluded. This setting is per-thread. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> --- Notes: v5: - Rename gcr_incl to gcr_user_incl (there will be a subsequent gcr_kernel when support for in-kernel MTE is added). v2: - Switch from an exclude mask to an include one for the prctl() interface. - Reset the allowed tags mask during flush_thread(). arch/arm64/include/asm/processor.h | 1 + arch/arm64/include/asm/sysreg.h | 7 ++++++ arch/arm64/kernel/mte.c | 35 +++++++++++++++++++++++++++--- arch/arm64/kernel/process.c | 2 +- include/uapi/linux/prctl.h | 3 +++ 5 files changed, 44 insertions(+), 4 deletions(-) diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h index 80e7f0573309..e1b1c2a6086e 100644 --- a/arch/arm64/include/asm/processor.h +++ b/arch/arm64/include/asm/processor.h @@ -153,6 +153,7 @@ struct thread_struct { #endif #ifdef CONFIG_ARM64_MTE u64 sctlr_tcf0; + u64 gcr_user_incl; #endif }; diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 2e12d8049d1c..d6357c4ea015 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -1033,6 +1033,13 @@ write_sysreg(__scs_new, sysreg); \ } while (0) +#define sysreg_clear_set_s(sysreg, clear, set) do { \ + u64 __scs_val = read_sysreg_s(sysreg); \ + u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set); \ + if (__scs_new != __scs_val) \ + write_sysreg_s(__scs_new, sysreg); \ +} while (0) + #endif #endif /* __ASM_SYSREG_H */ diff --git a/arch/arm64/kernel/mte.c b/arch/arm64/kernel/mte.c index 375483a1f573..07798b8d5039 100644 --- a/arch/arm64/kernel/mte.c +++ b/arch/arm64/kernel/mte.c @@ -71,6 +71,25 @@ static void set_sctlr_el1_tcf0(u64 tcf0) preempt_enable(); } +static void update_gcr_el1_excl(u64 incl) +{ + u64 excl = ~incl & SYS_GCR_EL1_EXCL_MASK; + + /* + * Note that 'incl' is an include mask (controlled by the user via + * prctl()) while GCR_EL1 accepts an exclude mask. + * No need for ISB since this only affects EL0 currently, implicit + * with ERET. + */ + sysreg_clear_set_s(SYS_GCR_EL1, SYS_GCR_EL1_EXCL_MASK, excl); +} + +static void set_gcr_el1_excl(u64 incl) +{ + current->thread.gcr_user_incl = incl; + update_gcr_el1_excl(incl); +} + void flush_mte_state(void) { if (!system_supports_mte()) @@ -82,6 +101,8 @@ void flush_mte_state(void) clear_thread_flag(TIF_MTE_ASYNC_FAULT); /* disable tag checking */ set_sctlr_el1_tcf0(SCTLR_EL1_TCF0_NONE); + /* reset tag generation mask */ + set_gcr_el1_excl(0); } void mte_thread_switch(struct task_struct *next) @@ -92,6 +113,7 @@ void mte_thread_switch(struct task_struct *next) /* avoid expensive SCTLR_EL1 accesses if no change */ if (current->thread.sctlr_tcf0 != next->thread.sctlr_tcf0) update_sctlr_el1_tcf0(next->thread.sctlr_tcf0); + update_gcr_el1_excl(next->thread.gcr_user_incl); } long set_mte_ctrl(unsigned long arg) @@ -116,23 +138,30 @@ long set_mte_ctrl(unsigned long arg) } set_sctlr_el1_tcf0(tcf0); + set_gcr_el1_excl((arg & PR_MTE_TAG_MASK) >> PR_MTE_TAG_SHIFT); return 0; } long get_mte_ctrl(void) { + unsigned long ret; + if (!system_supports_mte()) return 0; + ret = current->thread.gcr_user_incl << PR_MTE_TAG_SHIFT; + switch (current->thread.sctlr_tcf0) { case SCTLR_EL1_TCF0_NONE: return PR_MTE_TCF_NONE; case SCTLR_EL1_TCF0_SYNC: - return PR_MTE_TCF_SYNC; + ret |= PR_MTE_TCF_SYNC; + break; case SCTLR_EL1_TCF0_ASYNC: - return PR_MTE_TCF_ASYNC; + ret |= PR_MTE_TCF_ASYNC; + break; } - return 0; + return ret; } diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c index d19ce8053a03..b5c1c975d38e 100644 --- a/arch/arm64/kernel/process.c +++ b/arch/arm64/kernel/process.c @@ -616,7 +616,7 @@ long set_tagged_addr_ctrl(unsigned long arg) return -EINVAL; if (system_supports_mte()) - valid_mask |= PR_MTE_TCF_MASK; + valid_mask |= PR_MTE_TCF_MASK | PR_MTE_TAG_MASK; if (arg & ~valid_mask) return -EINVAL; diff --git a/include/uapi/linux/prctl.h b/include/uapi/linux/prctl.h index 2390ab324afa..7f0827705c9a 100644 --- a/include/uapi/linux/prctl.h +++ b/include/uapi/linux/prctl.h @@ -239,6 +239,9 @@ struct prctl_mm_map { # define PR_MTE_TCF_SYNC (1UL << PR_MTE_TCF_SHIFT) # define PR_MTE_TCF_ASYNC (2UL << PR_MTE_TCF_SHIFT) # define PR_MTE_TCF_MASK (3UL << PR_MTE_TCF_SHIFT) +/* MTE tag inclusion mask */ +# define PR_MTE_TAG_SHIFT 3 +# define PR_MTE_TAG_MASK (0xffffUL << PR_MTE_TAG_SHIFT) /* Control reclaim behavior when allocating memory */ #define PR_SET_IO_FLUSHER 57
WARNING: multiple messages have this Message-ID (diff)
From: Catalin Marinas <catalin.marinas@arm.com> To: linux-arm-kernel@lists.infradead.org Cc: linux-arch@vger.kernel.org, Szabolcs Nagy <szabolcs.nagy@arm.com>, Andrey Konovalov <andreyknvl@google.com>, Kevin Brodsky <kevin.brodsky@arm.com>, Peter Collingbourne <pcc@google.com>, linux-mm@kvack.org, Andrew Morton <akpm@linux-foundation.org>, Vincenzo Frascino <vincenzo.frascino@arm.com>, Will Deacon <will@kernel.org>, Dave P Martin <Dave.Martin@arm.com> Subject: [PATCH v6 18/26] arm64: mte: Allow user control of the generated random tags via prctl() Date: Fri, 3 Jul 2020 16:37:10 +0100 [thread overview] Message-ID: <20200703153718.16973-19-catalin.marinas@arm.com> (raw) In-Reply-To: <20200703153718.16973-1-catalin.marinas@arm.com> The IRG, ADDG and SUBG instructions insert a random tag in the resulting address. Certain tags can be excluded via the GCR_EL1.Exclude bitmap when, for example, the user wants a certain colour for freed buffers. Since the GCR_EL1 register is not accessible at EL0, extend the prctl(PR_SET_TAGGED_ADDR_CTRL) interface to include a 16-bit field in the first argument for controlling which tags can be generated by the above instruction (an include rather than exclude mask). Note that by default all non-zero tags are excluded. This setting is per-thread. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> --- Notes: v5: - Rename gcr_incl to gcr_user_incl (there will be a subsequent gcr_kernel when support for in-kernel MTE is added). v2: - Switch from an exclude mask to an include one for the prctl() interface. - Reset the allowed tags mask during flush_thread(). arch/arm64/include/asm/processor.h | 1 + arch/arm64/include/asm/sysreg.h | 7 ++++++ arch/arm64/kernel/mte.c | 35 +++++++++++++++++++++++++++--- arch/arm64/kernel/process.c | 2 +- include/uapi/linux/prctl.h | 3 +++ 5 files changed, 44 insertions(+), 4 deletions(-) diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h index 80e7f0573309..e1b1c2a6086e 100644 --- a/arch/arm64/include/asm/processor.h +++ b/arch/arm64/include/asm/processor.h @@ -153,6 +153,7 @@ struct thread_struct { #endif #ifdef CONFIG_ARM64_MTE u64 sctlr_tcf0; + u64 gcr_user_incl; #endif }; diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 2e12d8049d1c..d6357c4ea015 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -1033,6 +1033,13 @@ write_sysreg(__scs_new, sysreg); \ } while (0) +#define sysreg_clear_set_s(sysreg, clear, set) do { \ + u64 __scs_val = read_sysreg_s(sysreg); \ + u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set); \ + if (__scs_new != __scs_val) \ + write_sysreg_s(__scs_new, sysreg); \ +} while (0) + #endif #endif /* __ASM_SYSREG_H */ diff --git a/arch/arm64/kernel/mte.c b/arch/arm64/kernel/mte.c index 375483a1f573..07798b8d5039 100644 --- a/arch/arm64/kernel/mte.c +++ b/arch/arm64/kernel/mte.c @@ -71,6 +71,25 @@ static void set_sctlr_el1_tcf0(u64 tcf0) preempt_enable(); } +static void update_gcr_el1_excl(u64 incl) +{ + u64 excl = ~incl & SYS_GCR_EL1_EXCL_MASK; + + /* + * Note that 'incl' is an include mask (controlled by the user via + * prctl()) while GCR_EL1 accepts an exclude mask. + * No need for ISB since this only affects EL0 currently, implicit + * with ERET. + */ + sysreg_clear_set_s(SYS_GCR_EL1, SYS_GCR_EL1_EXCL_MASK, excl); +} + +static void set_gcr_el1_excl(u64 incl) +{ + current->thread.gcr_user_incl = incl; + update_gcr_el1_excl(incl); +} + void flush_mte_state(void) { if (!system_supports_mte()) @@ -82,6 +101,8 @@ void flush_mte_state(void) clear_thread_flag(TIF_MTE_ASYNC_FAULT); /* disable tag checking */ set_sctlr_el1_tcf0(SCTLR_EL1_TCF0_NONE); + /* reset tag generation mask */ + set_gcr_el1_excl(0); } void mte_thread_switch(struct task_struct *next) @@ -92,6 +113,7 @@ void mte_thread_switch(struct task_struct *next) /* avoid expensive SCTLR_EL1 accesses if no change */ if (current->thread.sctlr_tcf0 != next->thread.sctlr_tcf0) update_sctlr_el1_tcf0(next->thread.sctlr_tcf0); + update_gcr_el1_excl(next->thread.gcr_user_incl); } long set_mte_ctrl(unsigned long arg) @@ -116,23 +138,30 @@ long set_mte_ctrl(unsigned long arg) } set_sctlr_el1_tcf0(tcf0); + set_gcr_el1_excl((arg & PR_MTE_TAG_MASK) >> PR_MTE_TAG_SHIFT); return 0; } long get_mte_ctrl(void) { + unsigned long ret; + if (!system_supports_mte()) return 0; + ret = current->thread.gcr_user_incl << PR_MTE_TAG_SHIFT; + switch (current->thread.sctlr_tcf0) { case SCTLR_EL1_TCF0_NONE: return PR_MTE_TCF_NONE; case SCTLR_EL1_TCF0_SYNC: - return PR_MTE_TCF_SYNC; + ret |= PR_MTE_TCF_SYNC; + break; case SCTLR_EL1_TCF0_ASYNC: - return PR_MTE_TCF_ASYNC; + ret |= PR_MTE_TCF_ASYNC; + break; } - return 0; + return ret; } diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c index d19ce8053a03..b5c1c975d38e 100644 --- a/arch/arm64/kernel/process.c +++ b/arch/arm64/kernel/process.c @@ -616,7 +616,7 @@ long set_tagged_addr_ctrl(unsigned long arg) return -EINVAL; if (system_supports_mte()) - valid_mask |= PR_MTE_TCF_MASK; + valid_mask |= PR_MTE_TCF_MASK | PR_MTE_TAG_MASK; if (arg & ~valid_mask) return -EINVAL; diff --git a/include/uapi/linux/prctl.h b/include/uapi/linux/prctl.h index 2390ab324afa..7f0827705c9a 100644 --- a/include/uapi/linux/prctl.h +++ b/include/uapi/linux/prctl.h @@ -239,6 +239,9 @@ struct prctl_mm_map { # define PR_MTE_TCF_SYNC (1UL << PR_MTE_TCF_SHIFT) # define PR_MTE_TCF_ASYNC (2UL << PR_MTE_TCF_SHIFT) # define PR_MTE_TCF_MASK (3UL << PR_MTE_TCF_SHIFT) +/* MTE tag inclusion mask */ +# define PR_MTE_TAG_SHIFT 3 +# define PR_MTE_TAG_MASK (0xffffUL << PR_MTE_TAG_SHIFT) /* Control reclaim behavior when allocating memory */ #define PR_SET_IO_FLUSHER 57 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-07-03 15:38 UTC|newest] Thread overview: 78+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-07-03 15:36 [PATCH v6 00/26] arm64: Memory Tagging Extension user-space support Catalin Marinas 2020-07-03 15:36 ` Catalin Marinas 2020-07-03 15:36 ` [PATCH v6 01/26] arm64: mte: system register definitions Catalin Marinas 2020-07-03 15:36 ` Catalin Marinas 2020-07-03 15:36 ` [PATCH v6 02/26] arm64: mte: CPU feature detection and initial sysreg configuration Catalin Marinas 2020-07-03 15:36 ` Catalin Marinas 2020-07-13 10:08 ` Steven Price 2020-07-13 10:08 ` Steven Price 2020-07-13 17:45 ` Catalin Marinas 2020-07-13 17:45 ` Catalin Marinas 2020-07-03 15:36 ` [PATCH v6 03/26] arm64: mte: Use Normal Tagged attributes for the linear map Catalin Marinas 2020-07-03 15:36 ` Catalin Marinas 2020-07-03 15:36 ` [PATCH v6 04/26] arm64: mte: Add specific SIGSEGV codes Catalin Marinas 2020-07-03 15:36 ` Catalin Marinas 2020-07-03 15:36 ` [PATCH v6 05/26] arm64: mte: Handle synchronous and asynchronous tag check faults Catalin Marinas 2020-07-03 15:36 ` Catalin Marinas 2020-07-03 15:36 ` [PATCH v6 06/26] mm: Add PG_arch_2 page flag Catalin Marinas 2020-07-03 15:36 ` Catalin Marinas 2020-07-06 8:24 ` David Hildenbrand 2020-07-06 8:24 ` David Hildenbrand 2020-07-06 11:21 ` Catalin Marinas 2020-07-06 11:21 ` Catalin Marinas 2020-07-06 12:42 ` David Hildenbrand 2020-07-06 12:42 ` David Hildenbrand 2020-07-03 15:36 ` [PATCH v6 07/26] mm: Preserve the PG_arch_* flags in __split_huge_page_tail() Catalin Marinas 2020-07-03 15:36 ` Catalin Marinas 2020-07-06 14:16 ` David Hildenbrand 2020-07-06 14:16 ` David Hildenbrand 2020-07-06 16:30 ` Catalin Marinas 2020-07-06 16:30 ` Catalin Marinas 2020-07-06 17:56 ` David Hildenbrand 2020-07-06 17:56 ` David Hildenbrand 2020-07-08 12:17 ` Catalin Marinas 2020-07-08 12:17 ` Catalin Marinas 2020-07-03 15:37 ` [PATCH v6 08/26] arm64: mte: Clear the tags when a page is mapped in user-space with PROT_MTE Catalin Marinas 2020-07-03 15:37 ` Catalin Marinas 2020-07-03 15:37 ` [PATCH v6 09/26] arm64: mte: Tags-aware copy_{user_,}highpage() implementations Catalin Marinas 2020-07-03 15:37 ` [PATCH v6 09/26] arm64: mte: Tags-aware copy_{user_, }highpage() implementations Catalin Marinas 2020-07-03 15:37 ` [PATCH v6 10/26] arm64: Avoid unnecessary clear_user_page() indirection Catalin Marinas 2020-07-03 15:37 ` Catalin Marinas 2020-07-03 15:37 ` [PATCH v6 11/26] arm64: mte: Tags-aware aware memcmp_pages() implementation Catalin Marinas 2020-07-03 15:37 ` Catalin Marinas 2020-07-03 15:37 ` [PATCH v6 12/26] mm: Introduce arch_calc_vm_flag_bits() Catalin Marinas 2020-07-03 15:37 ` Catalin Marinas 2020-07-03 15:37 ` [PATCH v6 13/26] arm64: mte: Add PROT_MTE support to mmap() and mprotect() Catalin Marinas 2020-07-03 15:37 ` Catalin Marinas 2020-07-03 15:37 ` [PATCH v6 14/26] mm: Introduce arch_validate_flags() Catalin Marinas 2020-07-03 15:37 ` Catalin Marinas 2020-07-03 15:37 ` [PATCH v6 15/26] arm64: mte: Validate the PROT_MTE request via arch_validate_flags() Catalin Marinas 2020-07-03 15:37 ` Catalin Marinas 2020-07-03 15:37 ` [PATCH v6 16/26] mm: Allow arm64 mmap(PROT_MTE) on RAM-based files Catalin Marinas 2020-07-03 15:37 ` Catalin Marinas 2020-07-03 15:37 ` [PATCH v6 17/26] arm64: mte: Allow user control of the tag check mode via prctl() Catalin Marinas 2020-07-03 15:37 ` Catalin Marinas 2020-07-03 15:37 ` Catalin Marinas [this message] 2020-07-03 15:37 ` [PATCH v6 18/26] arm64: mte: Allow user control of the generated random tags " Catalin Marinas 2020-07-03 15:37 ` [PATCH v6 19/26] arm64: mte: Restore the GCR_EL1 register after a suspend Catalin Marinas 2020-07-03 15:37 ` Catalin Marinas 2020-07-03 15:37 ` [PATCH v6 20/26] arm64: mte: Add PTRACE_{PEEK,POKE}MTETAGS support Catalin Marinas 2020-07-03 15:37 ` Catalin Marinas 2020-07-09 14:41 ` Luis Machado 2020-07-09 14:41 ` Luis Machado 2020-07-03 15:37 ` [PATCH v6 21/26] fs: Handle intra-page faults in copy_mount_options() Catalin Marinas 2020-07-03 15:37 ` Catalin Marinas 2020-07-03 15:37 ` [PATCH v6 22/26] mm: Add arch hooks for saving/restoring tags Catalin Marinas 2020-07-03 15:37 ` Catalin Marinas 2020-07-03 15:37 ` [PATCH v6 23/26] arm64: mte: Enable swap of tagged pages Catalin Marinas 2020-07-03 15:37 ` Catalin Marinas 2020-07-03 15:37 ` [PATCH v6 24/26] arm64: mte: Save tags when hibernating Catalin Marinas 2020-07-03 15:37 ` Catalin Marinas 2020-07-03 15:37 ` [PATCH v6 25/26] arm64: mte: Kconfig entry Catalin Marinas 2020-07-03 15:37 ` Catalin Marinas 2020-07-03 15:37 ` [PATCH v6 26/26] arm64: mte: Add Memory Tagging Extension documentation Catalin Marinas 2020-07-03 15:37 ` Catalin Marinas 2020-07-09 9:32 ` Szabolcs Nagy 2020-07-09 9:32 ` Szabolcs Nagy 2020-07-09 14:43 ` Catalin Marinas 2020-07-09 14:43 ` Catalin Marinas
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