From: Mathieu Poirier <mathieu.poirier@linaro.org>
To: gregkh@linuxfoundation.org
Cc: saiprakash.ranjan@codeaurora.org, suzuki.poulose@arm.com,
vulab@iscas.ac.cn, tingwei@codeaurora.org,
andriy.shevchenko@linux.intel.com,
linux-arm-kernel@lists.infradead.org, mike.leach@linaro.org
Subject: [PATCH 17/17] coresight: etm4x: Fix save/restore during cpu idle
Date: Thu, 16 Jul 2020 11:57:46 -0600 [thread overview]
Message-ID: <20200716175746.3338735-18-mathieu.poirier@linaro.org> (raw)
In-Reply-To: <20200716175746.3338735-1-mathieu.poirier@linaro.org>
From: Suzuki K Poulose <suzuki.poulose@arm.com>
The ETM state save/restore incorrectly reads/writes some of the 64bit
registers (e.g, address comparators, vmid/cid comparators etc.) using
32bit accesses. Ensure we use the appropriate width accessors for
the registers.
Fixes: f188b5e76aae ("coresight: etm4x: Save/restore state across CPU low power states")
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Mike Leach <mike.leach@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
drivers/hwtracing/coresight/coresight-etm4x.c | 16 ++++++++--------
drivers/hwtracing/coresight/coresight-etm4x.h | 2 +-
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c
index 2d732af8b3e7..6d7d2169bfb2 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x.c
@@ -1206,8 +1206,8 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
}
for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
- state->trcacvr[i] = readl(drvdata->base + TRCACVRn(i));
- state->trcacatr[i] = readl(drvdata->base + TRCACATRn(i));
+ state->trcacvr[i] = readq(drvdata->base + TRCACVRn(i));
+ state->trcacatr[i] = readq(drvdata->base + TRCACATRn(i));
}
/*
@@ -1218,10 +1218,10 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
*/
for (i = 0; i < drvdata->numcidc; i++)
- state->trccidcvr[i] = readl(drvdata->base + TRCCIDCVRn(i));
+ state->trccidcvr[i] = readq(drvdata->base + TRCCIDCVRn(i));
for (i = 0; i < drvdata->numvmidc; i++)
- state->trcvmidcvr[i] = readl(drvdata->base + TRCVMIDCVRn(i));
+ state->trcvmidcvr[i] = readq(drvdata->base + TRCVMIDCVRn(i));
state->trccidcctlr0 = readl(drvdata->base + TRCCIDCCTLR0);
state->trccidcctlr1 = readl(drvdata->base + TRCCIDCCTLR1);
@@ -1319,18 +1319,18 @@ static void etm4_cpu_restore(struct etmv4_drvdata *drvdata)
}
for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
- writel_relaxed(state->trcacvr[i],
+ writeq_relaxed(state->trcacvr[i],
drvdata->base + TRCACVRn(i));
- writel_relaxed(state->trcacatr[i],
+ writeq_relaxed(state->trcacatr[i],
drvdata->base + TRCACATRn(i));
}
for (i = 0; i < drvdata->numcidc; i++)
- writel_relaxed(state->trccidcvr[i],
+ writeq_relaxed(state->trccidcvr[i],
drvdata->base + TRCCIDCVRn(i));
for (i = 0; i < drvdata->numvmidc; i++)
- writel_relaxed(state->trcvmidcvr[i],
+ writeq_relaxed(state->trcvmidcvr[i],
drvdata->base + TRCVMIDCVRn(i));
writel_relaxed(state->trccidcctlr0, drvdata->base + TRCCIDCCTLR0);
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
index 7da022e87218..b8283e1d6d88 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.h
+++ b/drivers/hwtracing/coresight/coresight-etm4x.h
@@ -334,7 +334,7 @@ struct etmv4_save_state {
u64 trcacvr[ETM_MAX_SINGLE_ADDR_CMP];
u64 trcacatr[ETM_MAX_SINGLE_ADDR_CMP];
u64 trccidcvr[ETMv4_MAX_CTXID_CMP];
- u32 trcvmidcvr[ETM_MAX_VMID_CMP];
+ u64 trcvmidcvr[ETM_MAX_VMID_CMP];
u32 trccidcctlr0;
u32 trccidcctlr1;
u32 trcvmidcctlr0;
--
2.25.1
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prev parent reply other threads:[~2020-07-16 18:05 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-16 17:57 [PATCH 00/17] coresight: next v5.8-rc5 Mathieu Poirier
2020-07-16 17:57 ` [PATCH 01/17] coresight: replicator: Use CS_AMBA_ID macro for id table Mathieu Poirier
2020-07-16 17:57 ` [PATCH 02/17] coresight: catu: " Mathieu Poirier
2020-07-16 17:57 ` [PATCH 03/17] coresight: etm4x: Add support to skip trace unit power up Mathieu Poirier
2020-07-16 17:57 ` [PATCH 04/17] dt-bindings: arm: coresight: " Mathieu Poirier
2020-07-16 17:57 ` [PATCH 05/17] coresight: replicator: Reset replicator if context is lost Mathieu Poirier
2020-07-16 17:57 ` [PATCH 06/17] dt-bindings: arm: coresight: Add optional property to replicators Mathieu Poirier
2020-07-16 17:57 ` [PATCH 07/17] coresight: Use devm_kcalloc() in coresight_alloc_conns() Mathieu Poirier
2020-07-16 17:57 ` [PATCH 08/17] coresight: Drop double check for ACPI companion device Mathieu Poirier
2020-07-16 17:57 ` [PATCH 09/17] coresight: etmv4: Fix resource selector constant Mathieu Poirier
2020-07-16 17:57 ` [PATCH 10/17] coresight: etmv4: Counter values not saved on disable Mathieu Poirier
2020-07-16 17:57 ` [PATCH 11/17] coresight: Fix comment in main header file Mathieu Poirier
2020-07-16 17:57 ` [PATCH 12/17] coresight: tmc: Add shutdown callback for TMC ETR Mathieu Poirier
2020-07-16 17:57 ` [PATCH 13/17] coresight: tmc: Fix TMC mode read in tmc_read_unprepare_etb() Mathieu Poirier
2020-07-16 17:57 ` [PATCH 14/17] coresight: Add default sink selection to CoreSight base Mathieu Poirier
2020-07-16 17:57 ` [PATCH 15/17] coresight: tmc: Update sink types for default selection Mathieu Poirier
2020-07-16 17:57 ` [PATCH 16/17] coresight: etm: perf: Add default sink selection to etm perf Mathieu Poirier
2020-07-16 17:57 ` Mathieu Poirier [this message]
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