From: Chen-Yu Tsai <wens@kernel.org> To: Maxime Ripard <mripard@kernel.org> Cc: Chen-Yu Tsai <wens@csie.org>, Rob Herring <robh+dt@kernel.org>, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 6/8] arm64: dts: allwinner: h5: Add CPU Operating Performance Points table Date: Sat, 18 Jul 2020 00:00:51 +0800 [thread overview] Message-ID: <20200717160053.31191-7-wens@kernel.org> (raw) In-Reply-To: <20200717160053.31191-1-wens@kernel.org> From: Chen-Yu Tsai <wens@csie.org> Add an OPP (Operating Performance Points) table for the CPU cores for boards to include to DVFS (Dynamic Voltage & Frequency Scaling) on the H5. The table originates from Armbian, but the maximum voltage is raised slightly to account for boards using slightly higher voltages. The table and tie in to the CPU cores are put in a separate dtsi file that board files can include to opt in. Or they can define their own tables if the standard one does not fit. This has been tested on the Libre Computer ALL-H3-CC-H5 and the Bananapi M2+ v1.2 H5, both with adequate cooling. The former has a fixed 1.2V regulator, while the latter has a GPIO controlled regulator switchable between 1.1V and 1.3V. Signed-off-by: Chen-Yu Tsai <wens@csie.org> --- Unfortunately I couldn't find the original source and author for the OPP table. So for now I put my name on it. If someone wants to claim authorship please do so. --- .../boot/dts/allwinner/sun50i-h5-cpu-opp.dtsi | 79 +++++++++++++++++++ 1 file changed, 79 insertions(+) create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h5-cpu-opp.dtsi diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-cpu-opp.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5-cpu-opp.dtsi new file mode 100644 index 000000000000..9d3a9fa78e2e --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-cpu-opp.dtsi @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (C) 2020 Chen-Yu Tsai <wens@csie.org> + +/ { + cpu_opp_table: opp_table { + compatible = "operating-points-v2"; + opp-shared; + + opp@408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <1000000 1000000 1310000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp@648000000 { + opp-hz = /bits/ 64 <648000000>; + opp-microvolt = <1040000 1040000 1310000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp@816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <1080000 1080000 1310000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp@912000000 { + opp-hz = /bits/ 64 <912000000>; + opp-microvolt = <1120000 1120000 1310000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp@960000000 { + opp-hz = /bits/ 64 <960000000>; + opp-microvolt = <1160000 1160000 1310000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp@1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <1200000 1200000 1310000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp@1056000000 { + opp-hz = /bits/ 64 <1056000000>; + opp-microvolt = <1240000 1240000 1310000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp@1104000000 { + opp-hz = /bits/ 64 <1104000000>; + opp-microvolt = <1260000 1260000 1310000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp@1152000000 { + opp-hz = /bits/ 64 <1152000000>; + opp-microvolt = <1300000 1300000 1310000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + }; +}; + +&cpu0 { + operating-points-v2 = <&cpu_opp_table>; +}; + +&cpu1 { + operating-points-v2 = <&cpu_opp_table>; +}; + +&cpu2 { + operating-points-v2 = <&cpu_opp_table>; +}; + +&cpu3 { + operating-points-v2 = <&cpu_opp_table>; +}; -- 2.27.0
WARNING: multiple messages have this Message-ID (diff)
From: Chen-Yu Tsai <wens@kernel.org> To: Maxime Ripard <mripard@kernel.org> Cc: devicetree@vger.kernel.org, Chen-Yu Tsai <wens@csie.org>, Rob Herring <robh+dt@kernel.org>, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 6/8] arm64: dts: allwinner: h5: Add CPU Operating Performance Points table Date: Sat, 18 Jul 2020 00:00:51 +0800 [thread overview] Message-ID: <20200717160053.31191-7-wens@kernel.org> (raw) In-Reply-To: <20200717160053.31191-1-wens@kernel.org> From: Chen-Yu Tsai <wens@csie.org> Add an OPP (Operating Performance Points) table for the CPU cores for boards to include to DVFS (Dynamic Voltage & Frequency Scaling) on the H5. The table originates from Armbian, but the maximum voltage is raised slightly to account for boards using slightly higher voltages. The table and tie in to the CPU cores are put in a separate dtsi file that board files can include to opt in. Or they can define their own tables if the standard one does not fit. This has been tested on the Libre Computer ALL-H3-CC-H5 and the Bananapi M2+ v1.2 H5, both with adequate cooling. The former has a fixed 1.2V regulator, while the latter has a GPIO controlled regulator switchable between 1.1V and 1.3V. Signed-off-by: Chen-Yu Tsai <wens@csie.org> --- Unfortunately I couldn't find the original source and author for the OPP table. So for now I put my name on it. If someone wants to claim authorship please do so. --- .../boot/dts/allwinner/sun50i-h5-cpu-opp.dtsi | 79 +++++++++++++++++++ 1 file changed, 79 insertions(+) create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h5-cpu-opp.dtsi diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-cpu-opp.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5-cpu-opp.dtsi new file mode 100644 index 000000000000..9d3a9fa78e2e --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-cpu-opp.dtsi @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (C) 2020 Chen-Yu Tsai <wens@csie.org> + +/ { + cpu_opp_table: opp_table { + compatible = "operating-points-v2"; + opp-shared; + + opp@408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <1000000 1000000 1310000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp@648000000 { + opp-hz = /bits/ 64 <648000000>; + opp-microvolt = <1040000 1040000 1310000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp@816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <1080000 1080000 1310000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp@912000000 { + opp-hz = /bits/ 64 <912000000>; + opp-microvolt = <1120000 1120000 1310000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp@960000000 { + opp-hz = /bits/ 64 <960000000>; + opp-microvolt = <1160000 1160000 1310000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp@1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <1200000 1200000 1310000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp@1056000000 { + opp-hz = /bits/ 64 <1056000000>; + opp-microvolt = <1240000 1240000 1310000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp@1104000000 { + opp-hz = /bits/ 64 <1104000000>; + opp-microvolt = <1260000 1260000 1310000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp@1152000000 { + opp-hz = /bits/ 64 <1152000000>; + opp-microvolt = <1300000 1300000 1310000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + }; +}; + +&cpu0 { + operating-points-v2 = <&cpu_opp_table>; +}; + +&cpu1 { + operating-points-v2 = <&cpu_opp_table>; +}; + +&cpu2 { + operating-points-v2 = <&cpu_opp_table>; +}; + +&cpu3 { + operating-points-v2 = <&cpu_opp_table>; +}; -- 2.27.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-07-17 16:01 UTC|newest] Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-07-17 16:00 [PATCH v2 0/8] arm64: dts: allwinner: h5: Enable CPU DVFS (cpufreq) Chen-Yu Tsai 2020-07-17 16:00 ` Chen-Yu Tsai 2020-07-17 16:00 ` [PATCH v2 1/8] ARM: dts: sunxi: libretech-all-h3-cc: Add regulator supply to all CPU cores Chen-Yu Tsai 2020-07-17 16:00 ` Chen-Yu Tsai 2020-07-17 16:00 ` [PATCH v2 2/8] ARM: dts: sunxi: bananapi-m2-plus-v1.2: " Chen-Yu Tsai 2020-07-17 16:00 ` Chen-Yu Tsai 2020-07-17 16:00 ` [PATCH v2 3/8] ARM: dts: sunxi: bananapi-m2-plus-v1.2: Fix CPU supply voltages Chen-Yu Tsai 2020-07-17 16:00 ` Chen-Yu Tsai 2020-07-17 16:00 ` [PATCH v2 4/8] arm64: dts: allwinner: h5: Add clock to CPU cores Chen-Yu Tsai 2020-07-17 16:00 ` Chen-Yu Tsai 2020-07-17 16:00 ` [PATCH v2 5/8] arm64: dts: allwinner: h5: Add trip and cooling maps to CPU thermal zones Chen-Yu Tsai 2020-07-17 16:00 ` Chen-Yu Tsai 2020-07-17 16:00 ` Chen-Yu Tsai [this message] 2020-07-17 16:00 ` [PATCH v2 6/8] arm64: dts: allwinner: h5: Add CPU Operating Performance Points table Chen-Yu Tsai 2020-07-17 16:00 ` [PATCH v2 7/8] arm64: dts: allwinner: h5: libretech-all-h3-cc: Tie in CPU OPPs Chen-Yu Tsai 2020-07-17 16:00 ` Chen-Yu Tsai 2020-07-17 16:00 ` [PATCH v2 8/8] arm64: dts: allwinner: h5: bananapi-m2-plus-v1.2: " Chen-Yu Tsai 2020-07-17 16:00 ` Chen-Yu Tsai 2020-07-20 14:11 ` [PATCH v2 0/8] arm64: dts: allwinner: h5: Enable CPU DVFS (cpufreq) Maxime Ripard 2020-07-20 14:11 ` Maxime Ripard
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