From: Ravi Bangoria <ravi.bangoria@linux.ibm.com>
To: mpe@ellerman.id.au, mikey@neuling.org
Cc: ravi.bangoria@linux.ibm.com, paulus@samba.org, npiggin@gmail.com,
christophe.leroy@c-s.fr, naveen.n.rao@linux.vnet.ibm.com,
peterz@infradead.org, jolsa@kernel.org, oleg@redhat.com,
fweisbec@gmail.com, mingo@kernel.org, pedromfc@br.ibm.com,
miltonm@us.ibm.com, jniethe5@gmail.com, rogealve@br.ibm.com,
linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org
Subject: [PATCH v5 03/10] powerpc/watchpoint: Fix DAWR exception for CACHEOP
Date: Thu, 23 Jul 2020 14:38:06 +0530 [thread overview]
Message-ID: <20200723090813.303838-4-ravi.bangoria@linux.ibm.com> (raw)
In-Reply-To: <20200723090813.303838-1-ravi.bangoria@linux.ibm.com>
'ea' returned by analyse_instr() needs to be aligned down to cache
block size for CACHEOP instructions. analyse_instr() does not set
size for CACHEOP, thus size also needs to be calculated manually.
Fixes: 27985b2a640e ("powerpc/watchpoint: Don't ignore extraneous exceptions blindly")
Fixes: 74c6881019b7 ("powerpc/watchpoint: Prepare handler to handle more than one watchpoint")
Signed-off-by: Ravi Bangoria <ravi.bangoria@linux.ibm.com>
---
arch/powerpc/kernel/hw_breakpoint.c | 21 ++++++++++++++++++++-
1 file changed, 20 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/kernel/hw_breakpoint.c b/arch/powerpc/kernel/hw_breakpoint.c
index a971e22aea81..c55e67bab271 100644
--- a/arch/powerpc/kernel/hw_breakpoint.c
+++ b/arch/powerpc/kernel/hw_breakpoint.c
@@ -538,7 +538,12 @@ static bool check_dawrx_constraints(struct pt_regs *regs, int type,
if (OP_IS_LOAD(type) && !(info->type & HW_BRK_TYPE_READ))
return false;
- if (OP_IS_STORE(type) && !(info->type & HW_BRK_TYPE_WRITE))
+ /*
+ * The Cache Management instructions other than dcbz never
+ * cause a match. i.e. if type is CACHEOP, the instruction
+ * is dcbz, and dcbz is treated as Store.
+ */
+ if ((OP_IS_STORE(type) || type == CACHEOP) && !(info->type & HW_BRK_TYPE_WRITE))
return false;
if (is_kernel_addr(regs->nip) && !(info->type & HW_BRK_TYPE_KERNEL))
@@ -601,6 +606,15 @@ static bool check_constraints(struct pt_regs *regs, struct ppc_inst instr,
return false;
}
+static int cache_op_size(void)
+{
+#ifdef __powerpc64__
+ return ppc64_caches.l1d.block_size;
+#else
+ return L1_CACHE_BYTES;
+#endif
+}
+
static void get_instr_detail(struct pt_regs *regs, struct ppc_inst *instr,
int *type, int *size, unsigned long *ea)
{
@@ -616,7 +630,12 @@ static void get_instr_detail(struct pt_regs *regs, struct ppc_inst *instr,
if (!(regs->msr & MSR_64BIT))
*ea &= 0xffffffffUL;
#endif
+
*size = GETSIZE(op.type);
+ if (*type == CACHEOP) {
+ *size = cache_op_size();
+ *ea &= ~(*size - 1);
+ }
}
static bool is_larx_stcx_instr(int type)
--
2.26.2
WARNING: multiple messages have this Message-ID (diff)
From: Ravi Bangoria <ravi.bangoria@linux.ibm.com>
To: mpe@ellerman.id.au, mikey@neuling.org
Cc: christophe.leroy@c-s.fr, ravi.bangoria@linux.ibm.com,
rogealve@br.ibm.com, miltonm@us.ibm.com, peterz@infradead.org,
fweisbec@gmail.com, oleg@redhat.com, npiggin@gmail.com,
linux-kernel@vger.kernel.org, paulus@samba.org, jolsa@kernel.org,
jniethe5@gmail.com, pedromfc@br.ibm.com,
naveen.n.rao@linux.vnet.ibm.com, linuxppc-dev@lists.ozlabs.org,
mingo@kernel.org
Subject: [PATCH v5 03/10] powerpc/watchpoint: Fix DAWR exception for CACHEOP
Date: Thu, 23 Jul 2020 14:38:06 +0530 [thread overview]
Message-ID: <20200723090813.303838-4-ravi.bangoria@linux.ibm.com> (raw)
In-Reply-To: <20200723090813.303838-1-ravi.bangoria@linux.ibm.com>
'ea' returned by analyse_instr() needs to be aligned down to cache
block size for CACHEOP instructions. analyse_instr() does not set
size for CACHEOP, thus size also needs to be calculated manually.
Fixes: 27985b2a640e ("powerpc/watchpoint: Don't ignore extraneous exceptions blindly")
Fixes: 74c6881019b7 ("powerpc/watchpoint: Prepare handler to handle more than one watchpoint")
Signed-off-by: Ravi Bangoria <ravi.bangoria@linux.ibm.com>
---
arch/powerpc/kernel/hw_breakpoint.c | 21 ++++++++++++++++++++-
1 file changed, 20 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/kernel/hw_breakpoint.c b/arch/powerpc/kernel/hw_breakpoint.c
index a971e22aea81..c55e67bab271 100644
--- a/arch/powerpc/kernel/hw_breakpoint.c
+++ b/arch/powerpc/kernel/hw_breakpoint.c
@@ -538,7 +538,12 @@ static bool check_dawrx_constraints(struct pt_regs *regs, int type,
if (OP_IS_LOAD(type) && !(info->type & HW_BRK_TYPE_READ))
return false;
- if (OP_IS_STORE(type) && !(info->type & HW_BRK_TYPE_WRITE))
+ /*
+ * The Cache Management instructions other than dcbz never
+ * cause a match. i.e. if type is CACHEOP, the instruction
+ * is dcbz, and dcbz is treated as Store.
+ */
+ if ((OP_IS_STORE(type) || type == CACHEOP) && !(info->type & HW_BRK_TYPE_WRITE))
return false;
if (is_kernel_addr(regs->nip) && !(info->type & HW_BRK_TYPE_KERNEL))
@@ -601,6 +606,15 @@ static bool check_constraints(struct pt_regs *regs, struct ppc_inst instr,
return false;
}
+static int cache_op_size(void)
+{
+#ifdef __powerpc64__
+ return ppc64_caches.l1d.block_size;
+#else
+ return L1_CACHE_BYTES;
+#endif
+}
+
static void get_instr_detail(struct pt_regs *regs, struct ppc_inst *instr,
int *type, int *size, unsigned long *ea)
{
@@ -616,7 +630,12 @@ static void get_instr_detail(struct pt_regs *regs, struct ppc_inst *instr,
if (!(regs->msr & MSR_64BIT))
*ea &= 0xffffffffUL;
#endif
+
*size = GETSIZE(op.type);
+ if (*type == CACHEOP) {
+ *size = cache_op_size();
+ *ea &= ~(*size - 1);
+ }
}
static bool is_larx_stcx_instr(int type)
--
2.26.2
next prev parent reply other threads:[~2020-07-23 9:09 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-23 9:08 [PATCH v5 00/10] powerpc/watchpoint: Enable 2nd DAWR on baremetal and powervm Ravi Bangoria
2020-07-23 9:08 ` Ravi Bangoria
2020-07-23 9:08 ` [PATCH v5 01/10] powerpc/watchpoint: Fix 512 byte boundary limit Ravi Bangoria
2020-07-23 9:08 ` Ravi Bangoria
2020-07-23 9:08 ` [PATCH v5 02/10] powerpc/watchpoint: Fix DAWR exception constraint Ravi Bangoria
2020-07-23 9:08 ` Ravi Bangoria
2020-07-23 9:08 ` Ravi Bangoria [this message]
2020-07-23 9:08 ` [PATCH v5 03/10] powerpc/watchpoint: Fix DAWR exception for CACHEOP Ravi Bangoria
2020-07-23 9:08 ` [PATCH v5 04/10] powerpc/watchpoint: Enable watchpoint functionality on power10 guest Ravi Bangoria
2020-07-23 9:08 ` Ravi Bangoria
2020-07-23 9:08 ` [PATCH v5 05/10] powerpc/dt_cpu_ftrs: Add feature for 2nd DAWR Ravi Bangoria
2020-07-23 9:08 ` Ravi Bangoria
2020-07-23 9:08 ` [PATCH v5 06/10] powerpc/watchpoint: Set CPU_FTR_DAWR1 based on pa-features bit Ravi Bangoria
2020-07-23 9:08 ` Ravi Bangoria
2020-07-23 9:08 ` [PATCH v5 07/10] powerpc/watchpoint: Rename current H_SET_MODE DAWR macro Ravi Bangoria
2020-07-23 9:08 ` Ravi Bangoria
2020-07-23 9:08 ` [PATCH v5 08/10] powerpc/watchpoint: Guest support for 2nd DAWR hcall Ravi Bangoria
2020-07-23 9:08 ` Ravi Bangoria
2020-07-23 9:08 ` [PATCH v5 09/10] powerpc/watchpoint: Return available watchpoints dynamically Ravi Bangoria
2020-07-23 9:08 ` Ravi Bangoria
2020-07-23 9:08 ` [PATCH v5 10/10] powerpc/watchpoint: Remove 512 byte boundary Ravi Bangoria
2020-07-23 9:08 ` Ravi Bangoria
2020-07-27 7:26 ` [PATCH v5 00/10] powerpc/watchpoint: Enable 2nd DAWR on baremetal and powervm Michael Ellerman
2020-07-27 7:26 ` Michael Ellerman
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