[PATCH 0/2] Add L1 and L2 error detection for A53 and A57

From: Sascha Hauer <s.hauer@pengutronix.de>
To: linux-edac@vger.kernel.org
Cc: Borislav Petkov <bp@alien8.de>,
	Mauro Carvalho Chehab <mchehab@kernel.org>,
	Tony Luck <tony.luck@intel.com>,
	James Morse <james.morse@arm.com>,
	Robert Richter <rrichter@marvell.com>,
	York Sun <york.sun@nxp.com>,
	kernel@pengutronix.de, linux-arm-kernel@lists.infradead.org,
	Sascha Hauer <s.hauer@pengutronix.de>
Subject: [PATCH 0/2] Add L1 and L2 error detection for A53 and A57
Date: Thu, 13 Aug 2020 09:57:19 +0200	[thread overview]
Message-ID: <20200813075721.27981-1-s.hauer@pengutronix.de> (raw)

This driver is based on an earlier version from York Sun which can
be found here: https://lkml.org/lkml/2018/3/14/1203.

At that time the conclusion was that this driver is not suitable for
mainline as it used IMPLEMENTATION DEFINED CPU registers and also
NXP specific SMC calls. All this was used for the error injection only,
for error reporting it is not needed.

This is another try to get this driver to mainline. All error injection
code has been removed (though it has initially been used to test this
driver on an i.MX8 SoC), what's left is unfortunately not testable, but
also doesn't contain none of the doubtful code anymore.

Sascha Hauer (1):
  drivers/edac: Add L1 and L2 error detection for A53 and A57

York Sun (1):
  arm64: dts: ls104x: Add L1/L2 cache edac node

 .../bindings/edac/arm,cortex-a5x-edac.yaml    |  32 +++
 .../arm64/boot/dts/freescale/fsl-ls1043a.dtsi |   5 +
 .../arm64/boot/dts/freescale/fsl-ls1046a.dtsi |   5 +
 drivers/edac/Kconfig                          |   6 +
 drivers/edac/Makefile                         |   1 +
 drivers/edac/cortex_arm64_l1_l2.c             | 208 ++++++++++++++++++
 6 files changed, 257 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/edac/arm,cortex-a5x-edac.yaml
 create mode 100644 drivers/edac/cortex_arm64_l1_l2.c

-- 
2.28.0