From: Rob Herring <robh@kernel.org> To: Jim Quinlan <james.quinlan@broadcom.com> Cc: linux-pci@vger.kernel.org, Nicolas Saenz Julienne <nsaenzjulienne@suse.de>, Christoph Hellwig <hch@lst.de>, Robin Murphy <robin.murphy@arm.com>, bcm-kernel-feedback-list@broadcom.com, Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>, Bjorn Helgaas <bhelgaas@google.com>, Florian Fainelli <f.fainelli@gmail.com>, Philipp Zabel <p.zabel@pengutronix.de>, "moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE" <linux-rpi-kernel@lists.infradead.org>, "moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE" <linux-arm-kernel@lists.infradead.org>, open list <linux-kernel@vger.kernel.org> Subject: Re: [PATCH v11 06/11] PCI: brcmstb: Add control of rescal reset Date: Thu, 10 Sep 2020 10:09:06 -0600 [thread overview] Message-ID: <20200910160906.GA449597@bogus> (raw) In-Reply-To: <20200824193036.6033-7-james.quinlan@broadcom.com> On Mon, Aug 24, 2020 at 03:30:19PM -0400, Jim Quinlan wrote: > From: Jim Quinlan <jquinlan@broadcom.com> > > Some STB chips have a special purpose reset controller named RESCAL (reset > calibration). The PCIe HW can now control RESCAL to start and stop its > operation. On probe(), the RESCAL is deasserted and the driver goes > through the sequence of setting registers and reading status in order to > start the internal PHY that is required for the PCIe. > > Signed-off-by: Jim Quinlan <jquinlan@broadcom.com> > Acked-by: Florian Fainelli <f.fainelli@gmail.com> > --- > drivers/pci/controller/pcie-brcmstb.c | 82 ++++++++++++++++++++++++++- > 1 file changed, 81 insertions(+), 1 deletion(-) > > diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c > index acf2239b0251..041b8d109563 100644 > --- a/drivers/pci/controller/pcie-brcmstb.c > +++ b/drivers/pci/controller/pcie-brcmstb.c > @@ -23,6 +23,7 @@ > #include <linux/of_platform.h> > #include <linux/pci.h> > #include <linux/printk.h> > +#include <linux/reset.h> > #include <linux/sizes.h> > #include <linux/slab.h> > #include <linux/string.h> > @@ -158,6 +159,16 @@ > #define DATA_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_DATA]) > #define PCIE_RGR1_SW_INIT_1(pcie) (pcie->reg_offsets[RGR1_SW_INIT_1]) > > +/* Rescal registers */ > +#define PCIE_DVT_PMU_PCIE_PHY_CTRL 0xc700 > +#define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS 0x3 > +#define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_DIG_RESET_MASK 0x4 > +#define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_DIG_RESET_SHIFT 0x2 > +#define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_RESET_MASK 0x2 > +#define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_RESET_SHIFT 0x1 > +#define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_PWRDN_MASK 0x1 > +#define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_PWRDN_SHIFT 0x0 > + > enum { > RGR1_SW_INIT_1, > EXT_CFG_INDEX, > @@ -247,6 +258,7 @@ struct brcm_pcie { > const int *reg_offsets; > const int *reg_field_info; > enum pcie_type type; > + struct reset_control *rescal; > }; > > /* > @@ -965,6 +977,47 @@ static void brcm_pcie_enter_l23(struct brcm_pcie *pcie) > dev_err(pcie->dev, "failed to enter low-power link state\n"); > } > > +static int brcm_phy_cntl(struct brcm_pcie *pcie, const int start) > +{ > + static const u32 shifts[PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS] = { > + PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_PWRDN_SHIFT, > + PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_RESET_SHIFT, > + PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_DIG_RESET_SHIFT,}; > + static const u32 masks[PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS] = { > + PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_PWRDN_MASK, > + PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_RESET_MASK, > + PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_DIG_RESET_MASK,}; > + const int beg = start ? 0 : PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS - 1; > + const int end = start ? PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS : -1; > + u32 tmp, combined_mask = 0; > + u32 val = !!start; > + void __iomem *base = pcie->base; > + int i; > + > + for (i = beg; i != end; start ? i++ : i--) { > + tmp = readl(base + PCIE_DVT_PMU_PCIE_PHY_CTRL); > + tmp = (tmp & ~masks[i]) | ((val << shifts[i]) & masks[i]); > + writel(tmp, base + PCIE_DVT_PMU_PCIE_PHY_CTRL); > + usleep_range(50, 200); > + combined_mask |= masks[i]; > + } > + > + tmp = readl(base + PCIE_DVT_PMU_PCIE_PHY_CTRL); > + val = start ? combined_mask : 0; > + > + return (tmp & combined_mask) == val ? 0 : -EIO; > +} > + > +static inline int brcm_phy_start(struct brcm_pcie *pcie) > +{ > + return pcie->rescal ? brcm_phy_cntl(pcie, 1) : 0; > +} > + > +static inline int brcm_phy_stop(struct brcm_pcie *pcie) > +{ > + return pcie->rescal ? brcm_phy_cntl(pcie, 0) : 0; > +} > + > static void brcm_pcie_turn_off(struct brcm_pcie *pcie) > { > void __iomem *base = pcie->base; > @@ -992,11 +1045,15 @@ static void brcm_pcie_turn_off(struct brcm_pcie *pcie) > static int brcm_pcie_suspend(struct device *dev) > { > struct brcm_pcie *pcie = dev_get_drvdata(dev); > + int ret; > > brcm_pcie_turn_off(pcie); > + ret = brcm_phy_stop(pcie); > + if (ret) > + dev_err(pcie->dev, "failed to stop phy\n"); > clk_disable_unprepare(pcie->clk); > > - return 0; > + return ret; > } > > static int brcm_pcie_resume(struct device *dev) > @@ -1009,6 +1066,12 @@ static int brcm_pcie_resume(struct device *dev) > base = pcie->base; > clk_prepare_enable(pcie->clk); > > + ret = brcm_phy_start(pcie); > + if (ret) { > + dev_err(pcie->dev, "failed to start phy\n"); > + return ret; > + } > + > /* Take bridge out of reset so we can access the SERDES reg */ > brcm_pcie_bridge_sw_init_set(pcie, 0); > > @@ -1034,6 +1097,9 @@ static void __brcm_pcie_remove(struct brcm_pcie *pcie) > { > brcm_msi_remove(pcie); > brcm_pcie_turn_off(pcie); > + if (brcm_phy_stop(pcie)) > + dev_err(pcie->dev, "failed to stop phy\n"); > + reset_control_assert(pcie->rescal); > clk_disable_unprepare(pcie->clk); > } > > @@ -1112,6 +1178,20 @@ static int brcm_pcie_probe(struct platform_device *pdev) > dev_err(&pdev->dev, "could not enable clock\n"); > return ret; > } > + pcie->rescal = devm_reset_control_get_optional_shared(&pdev->dev, "rescal"); > + if (IS_ERR(pcie->rescal)) > + return PTR_ERR(pcie->rescal); > + > + ret = reset_control_deassert(pcie->rescal); > + if (ret) > + dev_err(&pdev->dev, "failed to deassert 'rescal'\n"); > + > + ret = brcm_phy_start(pcie); > + if (ret) { > + dev_err(pcie->dev, "failed to start phy\n"); 4 calls to brcm_phy_cntl() and 4 error prints. Move the error print to brcm_phy_cntl. > + reset_control_assert(pcie->rescal); > + return ret; > + } > > ret = brcm_pcie_setup(pcie); > if (ret) > -- > 2.17.1 >
WARNING: multiple messages have this Message-ID (diff)
From: Rob Herring <robh@kernel.org> To: Jim Quinlan <james.quinlan@broadcom.com> Cc: "moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE" <linux-arm-kernel@lists.infradead.org>, Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>, linux-pci@vger.kernel.org, open list <linux-kernel@vger.kernel.org>, Florian Fainelli <f.fainelli@gmail.com>, bcm-kernel-feedback-list@broadcom.com, "moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE" <linux-rpi-kernel@lists.infradead.org>, Philipp Zabel <p.zabel@pengutronix.de>, Bjorn Helgaas <bhelgaas@google.com>, Robin Murphy <robin.murphy@arm.com>, Christoph Hellwig <hch@lst.de>, Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Subject: Re: [PATCH v11 06/11] PCI: brcmstb: Add control of rescal reset Date: Thu, 10 Sep 2020 10:09:06 -0600 [thread overview] Message-ID: <20200910160906.GA449597@bogus> (raw) In-Reply-To: <20200824193036.6033-7-james.quinlan@broadcom.com> On Mon, Aug 24, 2020 at 03:30:19PM -0400, Jim Quinlan wrote: > From: Jim Quinlan <jquinlan@broadcom.com> > > Some STB chips have a special purpose reset controller named RESCAL (reset > calibration). The PCIe HW can now control RESCAL to start and stop its > operation. On probe(), the RESCAL is deasserted and the driver goes > through the sequence of setting registers and reading status in order to > start the internal PHY that is required for the PCIe. > > Signed-off-by: Jim Quinlan <jquinlan@broadcom.com> > Acked-by: Florian Fainelli <f.fainelli@gmail.com> > --- > drivers/pci/controller/pcie-brcmstb.c | 82 ++++++++++++++++++++++++++- > 1 file changed, 81 insertions(+), 1 deletion(-) > > diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c > index acf2239b0251..041b8d109563 100644 > --- a/drivers/pci/controller/pcie-brcmstb.c > +++ b/drivers/pci/controller/pcie-brcmstb.c > @@ -23,6 +23,7 @@ > #include <linux/of_platform.h> > #include <linux/pci.h> > #include <linux/printk.h> > +#include <linux/reset.h> > #include <linux/sizes.h> > #include <linux/slab.h> > #include <linux/string.h> > @@ -158,6 +159,16 @@ > #define DATA_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_DATA]) > #define PCIE_RGR1_SW_INIT_1(pcie) (pcie->reg_offsets[RGR1_SW_INIT_1]) > > +/* Rescal registers */ > +#define PCIE_DVT_PMU_PCIE_PHY_CTRL 0xc700 > +#define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS 0x3 > +#define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_DIG_RESET_MASK 0x4 > +#define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_DIG_RESET_SHIFT 0x2 > +#define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_RESET_MASK 0x2 > +#define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_RESET_SHIFT 0x1 > +#define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_PWRDN_MASK 0x1 > +#define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_PWRDN_SHIFT 0x0 > + > enum { > RGR1_SW_INIT_1, > EXT_CFG_INDEX, > @@ -247,6 +258,7 @@ struct brcm_pcie { > const int *reg_offsets; > const int *reg_field_info; > enum pcie_type type; > + struct reset_control *rescal; > }; > > /* > @@ -965,6 +977,47 @@ static void brcm_pcie_enter_l23(struct brcm_pcie *pcie) > dev_err(pcie->dev, "failed to enter low-power link state\n"); > } > > +static int brcm_phy_cntl(struct brcm_pcie *pcie, const int start) > +{ > + static const u32 shifts[PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS] = { > + PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_PWRDN_SHIFT, > + PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_RESET_SHIFT, > + PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_DIG_RESET_SHIFT,}; > + static const u32 masks[PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS] = { > + PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_PWRDN_MASK, > + PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_RESET_MASK, > + PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_DIG_RESET_MASK,}; > + const int beg = start ? 0 : PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS - 1; > + const int end = start ? PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS : -1; > + u32 tmp, combined_mask = 0; > + u32 val = !!start; > + void __iomem *base = pcie->base; > + int i; > + > + for (i = beg; i != end; start ? i++ : i--) { > + tmp = readl(base + PCIE_DVT_PMU_PCIE_PHY_CTRL); > + tmp = (tmp & ~masks[i]) | ((val << shifts[i]) & masks[i]); > + writel(tmp, base + PCIE_DVT_PMU_PCIE_PHY_CTRL); > + usleep_range(50, 200); > + combined_mask |= masks[i]; > + } > + > + tmp = readl(base + PCIE_DVT_PMU_PCIE_PHY_CTRL); > + val = start ? combined_mask : 0; > + > + return (tmp & combined_mask) == val ? 0 : -EIO; > +} > + > +static inline int brcm_phy_start(struct brcm_pcie *pcie) > +{ > + return pcie->rescal ? brcm_phy_cntl(pcie, 1) : 0; > +} > + > +static inline int brcm_phy_stop(struct brcm_pcie *pcie) > +{ > + return pcie->rescal ? brcm_phy_cntl(pcie, 0) : 0; > +} > + > static void brcm_pcie_turn_off(struct brcm_pcie *pcie) > { > void __iomem *base = pcie->base; > @@ -992,11 +1045,15 @@ static void brcm_pcie_turn_off(struct brcm_pcie *pcie) > static int brcm_pcie_suspend(struct device *dev) > { > struct brcm_pcie *pcie = dev_get_drvdata(dev); > + int ret; > > brcm_pcie_turn_off(pcie); > + ret = brcm_phy_stop(pcie); > + if (ret) > + dev_err(pcie->dev, "failed to stop phy\n"); > clk_disable_unprepare(pcie->clk); > > - return 0; > + return ret; > } > > static int brcm_pcie_resume(struct device *dev) > @@ -1009,6 +1066,12 @@ static int brcm_pcie_resume(struct device *dev) > base = pcie->base; > clk_prepare_enable(pcie->clk); > > + ret = brcm_phy_start(pcie); > + if (ret) { > + dev_err(pcie->dev, "failed to start phy\n"); > + return ret; > + } > + > /* Take bridge out of reset so we can access the SERDES reg */ > brcm_pcie_bridge_sw_init_set(pcie, 0); > > @@ -1034,6 +1097,9 @@ static void __brcm_pcie_remove(struct brcm_pcie *pcie) > { > brcm_msi_remove(pcie); > brcm_pcie_turn_off(pcie); > + if (brcm_phy_stop(pcie)) > + dev_err(pcie->dev, "failed to stop phy\n"); > + reset_control_assert(pcie->rescal); > clk_disable_unprepare(pcie->clk); > } > > @@ -1112,6 +1178,20 @@ static int brcm_pcie_probe(struct platform_device *pdev) > dev_err(&pdev->dev, "could not enable clock\n"); > return ret; > } > + pcie->rescal = devm_reset_control_get_optional_shared(&pdev->dev, "rescal"); > + if (IS_ERR(pcie->rescal)) > + return PTR_ERR(pcie->rescal); > + > + ret = reset_control_deassert(pcie->rescal); > + if (ret) > + dev_err(&pdev->dev, "failed to deassert 'rescal'\n"); > + > + ret = brcm_phy_start(pcie); > + if (ret) { > + dev_err(pcie->dev, "failed to start phy\n"); 4 calls to brcm_phy_cntl() and 4 error prints. Move the error print to brcm_phy_cntl. > + reset_control_assert(pcie->rescal); > + return ret; > + } > > ret = brcm_pcie_setup(pcie); > if (ret) > -- > 2.17.1 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-09-10 16:14 UTC|newest] Thread overview: 176+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-08-24 19:30 [PATCH v11 00/11] PCI: brcmstb: enable PCIe for STB chips Jim Quinlan 2020-08-24 19:30 ` Jim Quinlan 2020-08-24 19:30 ` Jim Quinlan 2020-08-24 19:30 ` Jim Quinlan via iommu 2020-08-24 19:30 ` Jim Quinlan 2020-08-24 19:30 ` Jim Quinlan 2020-08-24 19:30 ` [PATCH v11 01/11] PCI: brcmstb: PCIE_BRCMSTB depends on ARCH_BRCMSTB Jim Quinlan 2020-08-24 19:30 ` [PATCH v11 02/11] dt-bindings: PCI: Add bindings for more Brcmstb chips Jim Quinlan 2020-08-24 19:30 ` Jim Quinlan 2020-08-24 19:30 ` [PATCH v11 03/11] PCI: brcmstb: Add bcm7278 register info Jim Quinlan 2020-08-24 19:30 ` Jim Quinlan 2020-09-10 15:44 ` Rob Herring 2020-09-10 15:44 ` Rob Herring 2020-08-24 19:30 ` [PATCH v11 04/11] PCI: brcmstb: Add suspend and resume pm_ops Jim Quinlan 2020-08-24 19:30 ` Jim Quinlan 2020-09-10 15:56 ` Rob Herring 2020-09-10 15:56 ` Rob Herring 2020-09-10 16:42 ` Jim Quinlan 2020-09-10 16:42 ` Jim Quinlan 2020-09-10 18:50 ` Rob Herring 2020-09-10 18:50 ` Rob Herring 2020-09-10 18:54 ` Florian Fainelli 2020-09-10 18:54 ` Florian Fainelli 2020-09-10 19:05 ` Jim Quinlan 2020-09-10 19:05 ` Jim Quinlan 2020-09-10 19:07 ` Florian Fainelli 2020-09-10 19:07 ` Florian Fainelli 2020-09-10 19:09 ` Jim Quinlan 2020-09-10 19:09 ` Jim Quinlan 2020-09-10 18:47 ` Florian Fainelli 2020-09-10 18:47 ` Florian Fainelli 2020-08-24 19:30 ` [PATCH v11 05/11] PCI: brcmstb: Add bcm7278 PERST# support Jim Quinlan 2020-08-24 19:30 ` Jim Quinlan 2020-09-10 16:04 ` Rob Herring 2020-09-10 16:04 ` Rob Herring 2020-08-24 19:30 ` [PATCH v11 06/11] PCI: brcmstb: Add control of rescal reset Jim Quinlan 2020-08-24 19:30 ` Jim Quinlan 2020-09-08 13:32 ` Lorenzo Pieralisi 2020-09-08 13:32 ` Lorenzo Pieralisi 2020-09-10 16:09 ` Rob Herring [this message] 2020-09-10 16:09 ` Rob Herring 2020-08-24 19:30 ` [PATCH v11 07/11] device-mapping: Introduce DMA range map, supplanting dma_pfn_offset Jim Quinlan 2020-08-24 19:30 ` Jim Quinlan 2020-08-24 19:30 ` Jim Quinlan via iommu 2020-08-25 9:45 ` Andy Shevchenko 2020-08-25 9:45 ` Andy Shevchenko 2020-08-25 9:45 ` Andy Shevchenko 2020-08-25 15:37 ` Jim Quinlan 2020-08-25 15:37 ` Jim Quinlan 2020-08-25 15:37 ` Jim Quinlan via iommu 2020-09-01 8:24 ` Christoph Hellwig 2020-09-01 8:24 ` Christoph Hellwig 2020-09-02 15:02 ` Jim Quinlan 2020-09-02 15:02 ` Jim Quinlan 2020-09-02 15:02 ` Jim Quinlan via iommu 2020-09-03 16:06 ` Christoph Hellwig 2020-09-03 16:06 ` Christoph Hellwig 2020-09-07 15:18 ` Nicolas Saenz Julienne 2020-09-07 15:18 ` Nicolas Saenz Julienne 2020-09-07 15:18 ` Nicolas Saenz Julienne 2020-09-08 6:54 ` Christoph Hellwig 2020-09-08 6:54 ` Christoph Hellwig 2020-09-02 21:53 ` Nathan Chancellor 2020-09-02 21:53 ` Nathan Chancellor 2020-09-02 21:53 ` Nathan Chancellor 2020-09-02 22:11 ` Jim Quinlan 2020-09-02 22:11 ` Jim Quinlan 2020-09-02 22:11 ` Jim Quinlan via iommu 2020-09-02 22:38 ` Nathan Chancellor 2020-09-02 22:38 ` Nathan Chancellor 2020-09-02 22:38 ` Nathan Chancellor 2020-09-03 0:36 ` Florian Fainelli 2020-09-03 0:36 ` Florian Fainelli 2020-09-03 0:36 ` Florian Fainelli 2020-09-03 0:52 ` Nathan Chancellor 2020-09-03 0:52 ` Nathan Chancellor 2020-09-03 0:52 ` Nathan Chancellor 2020-09-03 17:32 ` Jim Quinlan 2020-09-03 17:32 ` Jim Quinlan 2020-09-03 17:32 ` Jim Quinlan via iommu 2020-09-07 15:01 ` Nicolas Saenz Julienne 2020-09-07 15:01 ` Nicolas Saenz Julienne 2020-09-07 15:01 ` Nicolas Saenz Julienne 2020-09-07 17:40 ` Jim Quinlan 2020-09-07 17:40 ` Jim Quinlan 2020-09-07 17:40 ` Jim Quinlan via iommu 2020-09-07 18:19 ` Nicolas Saenz Julienne 2020-09-07 18:19 ` Nicolas Saenz Julienne 2020-09-07 18:19 ` Nicolas Saenz Julienne 2020-09-08 6:59 ` Christoph Hellwig 2020-09-08 6:59 ` Christoph Hellwig 2020-09-08 7:29 ` Christoph Hellwig 2020-09-08 7:29 ` Christoph Hellwig 2020-09-08 7:32 ` Christoph Hellwig 2020-09-08 7:32 ` Christoph Hellwig 2020-09-08 9:43 ` Christoph Hellwig 2020-09-08 9:43 ` Christoph Hellwig 2020-09-08 11:20 ` Nicolas Saenz Julienne 2020-09-08 11:20 ` Nicolas Saenz Julienne 2020-09-08 11:20 ` Nicolas Saenz Julienne 2020-09-08 12:41 ` Christoph Hellwig 2020-09-08 12:41 ` Christoph Hellwig 2020-09-08 15:59 ` Jim Quinlan 2020-09-08 15:59 ` Jim Quinlan 2020-09-08 15:59 ` Jim Quinlan via iommu 2020-09-09 6:21 ` Nathan Chancellor 2020-09-09 6:21 ` Nathan Chancellor 2020-09-09 6:21 ` Nathan Chancellor 2020-09-08 6:58 ` Christoph Hellwig 2020-09-08 6:58 ` Christoph Hellwig 2020-08-24 19:30 ` [PATCH v11 08/11] PCI: brcmstb: Set additional internal memory DMA viewport sizes Jim Quinlan 2020-08-24 19:30 ` Jim Quinlan 2020-09-10 16:17 ` Rob Herring 2020-09-10 16:17 ` Rob Herring 2020-09-11 15:28 ` Jim Quinlan 2020-09-11 15:28 ` Jim Quinlan 2020-09-11 16:13 ` Rob Herring 2020-09-11 16:13 ` Rob Herring 2020-08-24 19:30 ` [PATCH v11 09/11] PCI: brcmstb: Accommodate MSI for older chips Jim Quinlan 2020-08-24 19:30 ` Jim Quinlan 2020-09-10 16:20 ` Rob Herring 2020-09-10 16:20 ` Rob Herring 2020-08-24 19:30 ` [PATCH v11 10/11] PCI: brcmstb: Set bus max burst size by chip type Jim Quinlan 2020-08-24 19:30 ` Jim Quinlan 2020-09-10 16:22 ` Rob Herring 2020-09-10 16:22 ` Rob Herring 2020-08-24 19:30 ` [PATCH v11 11/11] PCI: brcmstb: Add bcm7211, bcm7216, bcm7445, bcm7278 to match list Jim Quinlan 2020-08-24 19:30 ` Jim Quinlan 2020-09-10 16:23 ` Rob Herring 2020-09-10 16:23 ` Rob Herring 2020-08-25 17:40 ` [PATCH v11 00/11] PCI: brcmstb: enable PCIe for STB chips Florian Fainelli 2020-08-25 17:40 ` Florian Fainelli 2020-08-25 17:40 ` Florian Fainelli 2020-08-25 17:40 ` Florian Fainelli 2020-08-25 17:40 ` Florian Fainelli 2020-08-25 17:40 ` Florian Fainelli 2020-08-27 6:35 ` Christoph Hellwig 2020-08-27 6:35 ` Christoph Hellwig 2020-08-27 6:35 ` Christoph Hellwig 2020-08-27 6:35 ` Christoph Hellwig 2020-08-27 6:35 ` Christoph Hellwig 2020-08-27 13:29 ` Jim Quinlan 2020-08-27 13:29 ` Jim Quinlan 2020-08-27 13:29 ` Jim Quinlan 2020-08-27 13:29 ` Jim Quinlan via iommu 2020-08-27 13:29 ` Jim Quinlan 2020-08-27 13:29 ` Jim Quinlan 2020-09-07 9:16 ` Lorenzo Pieralisi 2020-09-07 9:16 ` Lorenzo Pieralisi 2020-09-07 9:16 ` Lorenzo Pieralisi 2020-09-07 9:16 ` Lorenzo Pieralisi 2020-09-07 9:16 ` Lorenzo Pieralisi 2020-09-07 9:16 ` Lorenzo Pieralisi 2020-09-07 17:43 ` Jim Quinlan 2020-09-07 17:43 ` Jim Quinlan 2020-09-07 17:43 ` Jim Quinlan 2020-09-07 17:43 ` Jim Quinlan via iommu 2020-09-07 17:43 ` Jim Quinlan 2020-09-07 17:43 ` Jim Quinlan 2020-09-07 18:29 ` Florian Fainelli 2020-09-07 18:29 ` Florian Fainelli 2020-09-07 18:29 ` Florian Fainelli 2020-09-07 18:29 ` Florian Fainelli 2020-09-07 18:29 ` Florian Fainelli 2020-09-07 18:29 ` Florian Fainelli 2020-09-08 10:42 ` Lorenzo Pieralisi 2020-09-08 10:42 ` Lorenzo Pieralisi 2020-09-08 10:42 ` Lorenzo Pieralisi 2020-09-08 10:42 ` Lorenzo Pieralisi 2020-09-08 10:42 ` Lorenzo Pieralisi 2020-09-08 10:42 ` Lorenzo Pieralisi 2020-09-08 12:20 ` Christoph Hellwig 2020-09-08 12:20 ` Christoph Hellwig 2020-09-08 12:20 ` Christoph Hellwig 2020-09-08 12:20 ` Christoph Hellwig 2020-09-08 12:20 ` Christoph Hellwig
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