From: Karthik B S <karthik.b.s@intel.com> To: intel-gfx@lists.freedesktop.org Cc: paulo.r.zanoni@intel.com, michel@daenzer.net, Karthik B S <karthik.b.s@intel.com>, dri-devel@lists.freedesktop.org, vandita.kulkarni@intel.com, uma.shankar@intel.com, daniel.vetter@intel.com, nicholas.kazlauskas@amd.com Subject: [PATCH v9 6/8] drm/i915: WA for platforms with double buffered address update enable bit Date: Wed, 16 Sep 2020 20:38:22 +0530 [thread overview] Message-ID: <20200916150824.15749-7-karthik.b.s@intel.com> (raw) In-Reply-To: <20200916150824.15749-1-karthik.b.s@intel.com> In Gen 9 and Gen 10 platforms, async address update enable bit is double buffered. Due to this, during the transition from async flip to sync flip we have to wait until this bit is updated before continuing with the normal commit for sync flip. v9: -Rename skl_toggle_async_sync() to skl_disable_async_flip_wa(). (Ville) -Place the declarations appropriately as per need. (Ville) -Take the lock before the reg read. (Ville) -Fix comment and formatting. (Ville) -Use IS_GEN_RANGE() for gen check. (Ville) -Move skl_disable_async_flip_wa() to intel_pre_plane_update(). (Ville) Signed-off-by: Karthik B S <karthik.b.s@intel.com> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> --- drivers/gpu/drm/i915/display/intel_display.c | 46 ++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 0f0bcbb00c7f..6f6edc581e14 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -6562,6 +6562,43 @@ static void intel_post_plane_update(struct intel_atomic_state *state, icl_wa_scalerclkgating(dev_priv, pipe, false); } +static void skl_disable_async_flip_wa(struct intel_atomic_state *state, + struct intel_crtc *crtc, + const struct intel_crtc_state *new_crtc_state) +{ + struct drm_i915_private *dev_priv = to_i915(state->base.dev); + struct intel_plane *plane; + struct intel_plane_state *new_plane_state; + int i; + + for_each_new_intel_plane_in_state(state, plane, new_plane_state, i) { + u32 update_mask = new_crtc_state->update_planes; + u32 plane_ctl, surf_addr; + enum plane_id plane_id; + unsigned long irqflags; + enum pipe pipe; + + if (crtc->pipe != plane->pipe || + !(update_mask & BIT(plane->id))) + continue; + + plane_id = plane->id; + pipe = plane->pipe; + + spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); + plane_ctl = intel_de_read_fw(dev_priv, PLANE_CTL(pipe, plane_id)); + surf_addr = intel_de_read_fw(dev_priv, PLANE_SURF(pipe, plane_id)); + + plane_ctl &= ~PLANE_CTL_ASYNC_FLIP; + + intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl); + intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), surf_addr); + spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); + } + + intel_wait_for_vblank(dev_priv, crtc->pipe); +} + static void intel_pre_plane_update(struct intel_atomic_state *state, struct intel_crtc *crtc) { @@ -6647,6 +6684,15 @@ static void intel_pre_plane_update(struct intel_atomic_state *state, */ if (IS_GEN(dev_priv, 2) && planes_disabling(old_crtc_state, new_crtc_state)) intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); + + /* + * WA for platforms where async address update enable bit + * is double buffered and only latched at start of vblank. + */ + if (old_crtc_state->uapi.async_flip && + !new_crtc_state->uapi.async_flip && + IS_GEN_RANGE(dev_priv, 9, 10)) + skl_disable_async_flip_wa(state, crtc, new_crtc_state); } static void intel_crtc_disable_planes(struct intel_atomic_state *state, -- 2.22.0 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
WARNING: multiple messages have this Message-ID (diff)
From: Karthik B S <karthik.b.s@intel.com> To: intel-gfx@lists.freedesktop.org Cc: paulo.r.zanoni@intel.com, michel@daenzer.net, dri-devel@lists.freedesktop.org, daniel.vetter@intel.com, harry.wentland@amd.com, nicholas.kazlauskas@amd.com Subject: [Intel-gfx] [PATCH v9 6/8] drm/i915: WA for platforms with double buffered address update enable bit Date: Wed, 16 Sep 2020 20:38:22 +0530 [thread overview] Message-ID: <20200916150824.15749-7-karthik.b.s@intel.com> (raw) In-Reply-To: <20200916150824.15749-1-karthik.b.s@intel.com> In Gen 9 and Gen 10 platforms, async address update enable bit is double buffered. Due to this, during the transition from async flip to sync flip we have to wait until this bit is updated before continuing with the normal commit for sync flip. v9: -Rename skl_toggle_async_sync() to skl_disable_async_flip_wa(). (Ville) -Place the declarations appropriately as per need. (Ville) -Take the lock before the reg read. (Ville) -Fix comment and formatting. (Ville) -Use IS_GEN_RANGE() for gen check. (Ville) -Move skl_disable_async_flip_wa() to intel_pre_plane_update(). (Ville) Signed-off-by: Karthik B S <karthik.b.s@intel.com> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> --- drivers/gpu/drm/i915/display/intel_display.c | 46 ++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 0f0bcbb00c7f..6f6edc581e14 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -6562,6 +6562,43 @@ static void intel_post_plane_update(struct intel_atomic_state *state, icl_wa_scalerclkgating(dev_priv, pipe, false); } +static void skl_disable_async_flip_wa(struct intel_atomic_state *state, + struct intel_crtc *crtc, + const struct intel_crtc_state *new_crtc_state) +{ + struct drm_i915_private *dev_priv = to_i915(state->base.dev); + struct intel_plane *plane; + struct intel_plane_state *new_plane_state; + int i; + + for_each_new_intel_plane_in_state(state, plane, new_plane_state, i) { + u32 update_mask = new_crtc_state->update_planes; + u32 plane_ctl, surf_addr; + enum plane_id plane_id; + unsigned long irqflags; + enum pipe pipe; + + if (crtc->pipe != plane->pipe || + !(update_mask & BIT(plane->id))) + continue; + + plane_id = plane->id; + pipe = plane->pipe; + + spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); + plane_ctl = intel_de_read_fw(dev_priv, PLANE_CTL(pipe, plane_id)); + surf_addr = intel_de_read_fw(dev_priv, PLANE_SURF(pipe, plane_id)); + + plane_ctl &= ~PLANE_CTL_ASYNC_FLIP; + + intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl); + intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), surf_addr); + spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); + } + + intel_wait_for_vblank(dev_priv, crtc->pipe); +} + static void intel_pre_plane_update(struct intel_atomic_state *state, struct intel_crtc *crtc) { @@ -6647,6 +6684,15 @@ static void intel_pre_plane_update(struct intel_atomic_state *state, */ if (IS_GEN(dev_priv, 2) && planes_disabling(old_crtc_state, new_crtc_state)) intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); + + /* + * WA for platforms where async address update enable bit + * is double buffered and only latched at start of vblank. + */ + if (old_crtc_state->uapi.async_flip && + !new_crtc_state->uapi.async_flip && + IS_GEN_RANGE(dev_priv, 9, 10)) + skl_disable_async_flip_wa(state, crtc, new_crtc_state); } static void intel_crtc_disable_planes(struct intel_atomic_state *state, -- 2.22.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2020-09-16 15:35 UTC|newest] Thread overview: 53+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-09-16 15:08 [PATCH v9 0/8] Asynchronous flip implementation for i915 Karthik B S 2020-09-16 15:08 ` [Intel-gfx] " Karthik B S 2020-09-16 15:08 ` [PATCH v9 1/8] drm/i915: Add enable/disable flip done and flip done handler Karthik B S 2020-09-16 15:08 ` [Intel-gfx] " Karthik B S 2020-09-16 15:08 ` [PATCH v9 2/8] drm/i915: Add support for async flips in I915 Karthik B S 2020-09-16 15:08 ` [Intel-gfx] " Karthik B S 2020-09-16 15:08 ` [PATCH v9 3/8] drm/i915: Add checks specific to async flips Karthik B S 2020-09-16 15:08 ` [Intel-gfx] " Karthik B S 2020-09-18 9:02 ` [PATCH v10 " Karthik B S 2020-09-18 9:02 ` [Intel-gfx] " Karthik B S 2020-09-18 11:51 ` Ville Syrjälä 2020-09-18 11:51 ` [Intel-gfx] " Ville Syrjälä 2020-09-21 10:49 ` Karthik B S 2020-09-21 10:49 ` [Intel-gfx] " Karthik B S 2020-09-16 15:08 ` [PATCH v9 4/8] drm/i915: Do not call drm_crtc_arm_vblank_event in " Karthik B S 2020-09-16 15:08 ` [Intel-gfx] " Karthik B S 2020-09-16 15:08 ` [PATCH v9 5/8] drm/i915: Add dedicated plane hook for async flip case Karthik B S 2020-09-16 15:08 ` [Intel-gfx] " Karthik B S 2020-09-18 7:00 ` [PATCH v10 " Karthik B S 2020-09-18 7:00 ` [Intel-gfx] " Karthik B S 2020-09-18 11:53 ` Ville Syrjälä 2020-09-18 11:53 ` [Intel-gfx] " Ville Syrjälä 2020-09-21 10:52 ` Karthik B S 2020-09-21 10:52 ` [Intel-gfx] " Karthik B S 2020-09-16 15:08 ` Karthik B S [this message] 2020-09-16 15:08 ` [Intel-gfx] [PATCH v9 6/8] drm/i915: WA for platforms with double buffered address update enable bit Karthik B S 2020-09-18 11:54 ` Ville Syrjälä 2020-09-18 11:54 ` [Intel-gfx] " Ville Syrjälä 2020-09-21 10:53 ` Karthik B S 2020-09-21 10:53 ` [Intel-gfx] " Karthik B S 2020-09-16 15:08 ` [PATCH v9 7/8] Documentation/gpu: Add asynchronous flip documentation for i915 Karthik B S 2020-09-16 15:08 ` [Intel-gfx] " Karthik B S 2020-09-18 11:58 ` Ville Syrjälä 2020-09-18 11:58 ` [Intel-gfx] " Ville Syrjälä 2020-09-21 10:55 ` Karthik B S 2020-09-21 10:55 ` [Intel-gfx] " Karthik B S 2020-09-16 15:08 ` [PATCH v9 8/8] drm/i915: Enable async flips in i915 Karthik B S 2020-09-16 15:08 ` [Intel-gfx] " Karthik B S 2020-09-18 12:03 ` Ville Syrjälä 2020-09-18 12:03 ` [Intel-gfx] " Ville Syrjälä 2020-09-21 10:59 ` Karthik B S 2020-09-21 10:59 ` [Intel-gfx] " Karthik B S 2020-09-16 15:46 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Asynchronous flip implementation for i915 (rev9) Patchwork 2020-09-16 15:48 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2020-09-16 16:11 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2020-09-16 21:27 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork 2020-09-18 7:55 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Asynchronous flip implementation for i915 (rev10) Patchwork 2020-09-18 7:56 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2020-09-18 8:20 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2020-09-18 9:26 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork 2020-09-18 9:58 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Asynchronous flip implementation for i915 (rev11) Patchwork 2020-09-18 10:22 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2020-09-18 12:17 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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