From: Will Deacon <will@kernel.org>
To: Robin Murphy <robin.murphy@arm.com>
Cc: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>,
freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org,
iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org,
Akhil P Oommen <akhilpo@codeaurora.org>,
dri-devel@lists.freedesktop.org,
"Kristian H . Kristensen" <hoegsberg@google.com>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCHv4 1/6] iommu/io-pgtable-arm: Add support to use system cache
Date: Mon, 21 Sep 2020 23:23:30 +0100 [thread overview]
Message-ID: <20200921222329.GA4409@willie-the-truck> (raw)
In-Reply-To: <9646dd4f-f1e6-992d-b8a0-0f2c14fa9fe8@arm.com>
On Mon, Sep 21, 2020 at 11:03:49PM +0100, Robin Murphy wrote:
> On 2020-09-21 19:03, Will Deacon wrote:
> > On Fri, Sep 11, 2020 at 07:57:18PM +0530, Sai Prakash Ranjan wrote:
> > > Add a quirk IO_PGTABLE_QUIRK_SYS_CACHE to override the
> > > attributes set in TCR for the page table walker when
> > > using system cache.
> >
> > I wonder if the panfrost folks can reuse this for the issue discussed
> > over at:
> >
> > https://lore.kernel.org/r/cover.1600213517.git.robin.murphy@arm.com
>
> Isn't this all hinged around the outer cacheability attribute, rather than
> shareability (since these are nominally NC mappings and thus already
> properly Osh)? The Panfrost issue is just about shareability domains being a
> bit wonky; the cacheability attributes there are actually reasonably normal
> (other than not having a non-cacheable type at all, only a choice of
> allocation policies...)
Hmm, yes, this quirk _also_ changes the cacheability settings which isn't
what we need. It's a bit grotty having two different ways to configure these
TCR bits (i.e. a quirk and a format), but at least the mali format rejects
all of the quirks so I suppose it's not the end of the world.
Will
WARNING: multiple messages have this Message-ID (diff)
From: Will Deacon <will@kernel.org>
To: Robin Murphy <robin.murphy@arm.com>
Cc: linux-arm-msm@vger.kernel.org,
Akhil P Oommen <akhilpo@codeaurora.org>,
dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org,
iommu@lists.linux-foundation.org,
"Kristian H . Kristensen" <hoegsberg@google.com>,
freedreno@lists.freedesktop.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCHv4 1/6] iommu/io-pgtable-arm: Add support to use system cache
Date: Mon, 21 Sep 2020 23:23:30 +0100 [thread overview]
Message-ID: <20200921222329.GA4409@willie-the-truck> (raw)
In-Reply-To: <9646dd4f-f1e6-992d-b8a0-0f2c14fa9fe8@arm.com>
On Mon, Sep 21, 2020 at 11:03:49PM +0100, Robin Murphy wrote:
> On 2020-09-21 19:03, Will Deacon wrote:
> > On Fri, Sep 11, 2020 at 07:57:18PM +0530, Sai Prakash Ranjan wrote:
> > > Add a quirk IO_PGTABLE_QUIRK_SYS_CACHE to override the
> > > attributes set in TCR for the page table walker when
> > > using system cache.
> >
> > I wonder if the panfrost folks can reuse this for the issue discussed
> > over at:
> >
> > https://lore.kernel.org/r/cover.1600213517.git.robin.murphy@arm.com
>
> Isn't this all hinged around the outer cacheability attribute, rather than
> shareability (since these are nominally NC mappings and thus already
> properly Osh)? The Panfrost issue is just about shareability domains being a
> bit wonky; the cacheability attributes there are actually reasonably normal
> (other than not having a non-cacheable type at all, only a choice of
> allocation policies...)
Hmm, yes, this quirk _also_ changes the cacheability settings which isn't
what we need. It's a bit grotty having two different ways to configure these
TCR bits (i.e. a quirk and a format), but at least the mali format rejects
all of the quirks so I suppose it's not the end of the world.
Will
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
WARNING: multiple messages have this Message-ID (diff)
From: Will Deacon <will@kernel.org>
To: Robin Murphy <robin.murphy@arm.com>
Cc: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>,
linux-arm-msm@vger.kernel.org,
Akhil P Oommen <akhilpo@codeaurora.org>,
dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org,
iommu@lists.linux-foundation.org,
"Kristian H . Kristensen" <hoegsberg@google.com>,
freedreno@lists.freedesktop.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCHv4 1/6] iommu/io-pgtable-arm: Add support to use system cache
Date: Mon, 21 Sep 2020 23:23:30 +0100 [thread overview]
Message-ID: <20200921222329.GA4409@willie-the-truck> (raw)
In-Reply-To: <9646dd4f-f1e6-992d-b8a0-0f2c14fa9fe8@arm.com>
On Mon, Sep 21, 2020 at 11:03:49PM +0100, Robin Murphy wrote:
> On 2020-09-21 19:03, Will Deacon wrote:
> > On Fri, Sep 11, 2020 at 07:57:18PM +0530, Sai Prakash Ranjan wrote:
> > > Add a quirk IO_PGTABLE_QUIRK_SYS_CACHE to override the
> > > attributes set in TCR for the page table walker when
> > > using system cache.
> >
> > I wonder if the panfrost folks can reuse this for the issue discussed
> > over at:
> >
> > https://lore.kernel.org/r/cover.1600213517.git.robin.murphy@arm.com
>
> Isn't this all hinged around the outer cacheability attribute, rather than
> shareability (since these are nominally NC mappings and thus already
> properly Osh)? The Panfrost issue is just about shareability domains being a
> bit wonky; the cacheability attributes there are actually reasonably normal
> (other than not having a non-cacheable type at all, only a choice of
> allocation policies...)
Hmm, yes, this quirk _also_ changes the cacheability settings which isn't
what we need. It's a bit grotty having two different ways to configure these
TCR bits (i.e. a quirk and a format), but at least the mali format rejects
all of the quirks so I suppose it's not the end of the world.
Will
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
WARNING: multiple messages have this Message-ID (diff)
From: Will Deacon <will@kernel.org>
To: Robin Murphy <robin.murphy@arm.com>
Cc: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>,
linux-arm-msm@vger.kernel.org,
Akhil P Oommen <akhilpo@codeaurora.org>,
dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org,
iommu@lists.linux-foundation.org,
"Kristian H . Kristensen" <hoegsberg@google.com>,
freedreno@lists.freedesktop.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCHv4 1/6] iommu/io-pgtable-arm: Add support to use system cache
Date: Mon, 21 Sep 2020 23:23:30 +0100 [thread overview]
Message-ID: <20200921222329.GA4409@willie-the-truck> (raw)
In-Reply-To: <9646dd4f-f1e6-992d-b8a0-0f2c14fa9fe8@arm.com>
On Mon, Sep 21, 2020 at 11:03:49PM +0100, Robin Murphy wrote:
> On 2020-09-21 19:03, Will Deacon wrote:
> > On Fri, Sep 11, 2020 at 07:57:18PM +0530, Sai Prakash Ranjan wrote:
> > > Add a quirk IO_PGTABLE_QUIRK_SYS_CACHE to override the
> > > attributes set in TCR for the page table walker when
> > > using system cache.
> >
> > I wonder if the panfrost folks can reuse this for the issue discussed
> > over at:
> >
> > https://lore.kernel.org/r/cover.1600213517.git.robin.murphy@arm.com
>
> Isn't this all hinged around the outer cacheability attribute, rather than
> shareability (since these are nominally NC mappings and thus already
> properly Osh)? The Panfrost issue is just about shareability domains being a
> bit wonky; the cacheability attributes there are actually reasonably normal
> (other than not having a non-cacheable type at all, only a choice of
> allocation policies...)
Hmm, yes, this quirk _also_ changes the cacheability settings which isn't
what we need. It's a bit grotty having two different ways to configure these
TCR bits (i.e. a quirk and a format), but at least the mali format rejects
all of the quirks so I suppose it's not the end of the world.
Will
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
next prev parent reply other threads:[~2020-09-21 22:23 UTC|newest]
Thread overview: 68+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <cover.1599832685.git.saiprakash.ranjan@codeaurora.org>
2020-09-11 14:27 ` [PATCHv4 1/6] iommu/io-pgtable-arm: Add support to use system cache Sai Prakash Ranjan
2020-09-11 14:27 ` Sai Prakash Ranjan
2020-09-11 14:27 ` Sai Prakash Ranjan
2020-09-11 14:27 ` Sai Prakash Ranjan
2020-09-11 14:27 ` [PATCHv4 2/6] iommu/arm-smmu: Add domain attribute for " Sai Prakash Ranjan
2020-09-11 14:27 ` Sai Prakash Ranjan
2020-09-11 14:27 ` Sai Prakash Ranjan
2020-09-11 14:27 ` Sai Prakash Ranjan
2020-09-11 14:28 ` [PATCHv4 3/6] drm/msm: rearrange the gpu_rmw() function Sai Prakash Ranjan
2020-09-11 14:28 ` Sai Prakash Ranjan
2020-09-11 14:28 ` Sai Prakash Ranjan
2020-09-11 14:28 ` Sai Prakash Ranjan
2020-09-11 14:28 ` [PATCHv4 4/6] drm/msm/a6xx: Add support for using system cache(LLC) Sai Prakash Ranjan
2020-09-11 14:28 ` Sai Prakash Ranjan
2020-09-11 14:28 ` Sai Prakash Ranjan
2020-09-11 14:28 ` Sai Prakash Ranjan
2020-09-11 14:28 ` [PATCHv4 5/6] iommu: arm-smmu-impl: Use table to list QCOM implementations Sai Prakash Ranjan
2020-09-11 14:28 ` Sai Prakash Ranjan
2020-09-11 14:28 ` Sai Prakash Ranjan
2020-09-11 14:28 ` Sai Prakash Ranjan
2020-09-11 14:28 ` [PATCHv4 6/6] iommu: arm-smmu-impl: Remove unwanted extra blank lines Sai Prakash Ranjan
2020-09-11 14:28 ` Sai Prakash Ranjan
2020-09-11 14:28 ` Sai Prakash Ranjan
2020-09-11 14:28 ` Sai Prakash Ranjan
[not found] ` <010101747d912d9f-c8050b8d-1e81-4be0-ac35-b221f657b490-000000@us-west-2.amazonses.com>
2020-09-11 16:03 ` Robin Murphy
2020-09-11 16:03 ` Robin Murphy
2020-09-11 16:03 ` Robin Murphy
2020-09-11 16:03 ` Robin Murphy
2020-09-11 16:07 ` Will Deacon
2020-09-11 16:07 ` Will Deacon
2020-09-11 16:07 ` Will Deacon
2020-09-11 16:07 ` Will Deacon
2020-09-11 16:21 ` Sai Prakash Ranjan
2020-09-11 16:34 ` Robin Murphy
2020-09-11 16:34 ` Robin Murphy
2020-09-11 16:34 ` Robin Murphy
2020-09-11 16:34 ` Robin Murphy
2020-09-11 16:50 ` Sai Prakash Ranjan
2020-09-11 16:50 ` Sai Prakash Ranjan
2020-09-11 16:50 ` Sai Prakash Ranjan
2020-09-11 16:50 ` Sai Prakash Ranjan
[not found] ` <a33160854744942f660fae691a4a30ec@codeaurora.org>
2020-09-15 6:58 ` Sai Prakash Ranjan
2020-09-15 6:58 ` Sai Prakash Ranjan
2020-09-15 6:58 ` Sai Prakash Ranjan
2020-09-15 6:58 ` Sai Prakash Ranjan
2020-09-11 16:21 ` Sai Prakash Ranjan
2020-09-11 16:21 ` Sai Prakash Ranjan
2020-09-11 16:21 ` Sai Prakash Ranjan
2020-09-11 16:19 ` Sai Prakash Ranjan
2020-09-11 16:19 ` Sai Prakash Ranjan
2020-09-11 16:19 ` Sai Prakash Ranjan
2020-09-11 16:19 ` Sai Prakash Ranjan
[not found] ` <3b1beb6cf6a34a44b0ecff9ec5a2105b5ff91bd4.1599832685.git.saiprakash.ranjan@codeaurora.org>
2020-09-21 18:03 ` [PATCHv4 1/6] iommu/io-pgtable-arm: Add support to use system cache Will Deacon
2020-09-21 18:03 ` Will Deacon
2020-09-21 18:03 ` Will Deacon
2020-09-21 18:03 ` Will Deacon
2020-09-21 22:03 ` Robin Murphy
2020-09-21 22:03 ` Robin Murphy
2020-09-21 22:03 ` Robin Murphy
2020-09-21 22:03 ` Robin Murphy
2020-09-21 22:23 ` Will Deacon [this message]
2020-09-21 22:23 ` Will Deacon
2020-09-21 22:23 ` Will Deacon
2020-09-21 22:23 ` Will Deacon
2020-09-22 6:23 ` Sai Prakash Ranjan
2020-09-22 6:23 ` Sai Prakash Ranjan
2020-09-22 6:23 ` Sai Prakash Ranjan
2020-09-22 6:23 ` Sai Prakash Ranjan
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