From: Adrian Ratiu <adrian.ratiu@collabora.com> To: Ezequiel Garcia <ezequiel@collabora.com>, Philipp Zabel <p.zabel@pengutronix.de> Cc: Mark Brown <broonie@kernel.org>, Mauro Carvalho Chehab <mchehab@kernel.org>, Fruehberger Peter <Peter.Fruehberger@de.bosch.com>, kuhanh.murugasen.krishnan@intel.com, Daniel Vetter <daniel@ffwll.ch>, kernel@collabora.com, linux-media@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 01/18] media: hantro: document all int reg bits up to vc8000 Date: Mon, 12 Oct 2020 23:59:40 +0300 [thread overview] Message-ID: <20201012205957.889185-2-adrian.ratiu@collabora.com> (raw) In-Reply-To: <20201012205957.889185-1-adrian.ratiu@collabora.com> These do not all strictly belong to the g1 core and even the majority of previously documented bits were not used (yet) by the driver irq handlers, but it's still very useful to have an overview of all IRQs, especially since starting with core versions vc8000 and later the irq bits previously used by G1 and G2 have been merged at the same address. Signed-off-by: Adrian Ratiu <adrian.ratiu@collabora.com> --- drivers/staging/media/hantro/hantro_g1_regs.h | 39 +++++++++++++------ 1 file changed, 28 insertions(+), 11 deletions(-) diff --git a/drivers/staging/media/hantro/hantro_g1_regs.h b/drivers/staging/media/hantro/hantro_g1_regs.h index c1756e3d5391..80ff297f6f68 100644 --- a/drivers/staging/media/hantro/hantro_g1_regs.h +++ b/drivers/staging/media/hantro/hantro_g1_regs.h @@ -13,17 +13,34 @@ /* Decoder registers. */ #define G1_REG_INTERRUPT 0x004 -#define G1_REG_INTERRUPT_DEC_PIC_INF BIT(24) -#define G1_REG_INTERRUPT_DEC_TIMEOUT BIT(18) -#define G1_REG_INTERRUPT_DEC_SLICE_INT BIT(17) -#define G1_REG_INTERRUPT_DEC_ERROR_INT BIT(16) -#define G1_REG_INTERRUPT_DEC_ASO_INT BIT(15) -#define G1_REG_INTERRUPT_DEC_BUFFER_INT BIT(14) -#define G1_REG_INTERRUPT_DEC_BUS_INT BIT(13) -#define G1_REG_INTERRUPT_DEC_RDY_INT BIT(12) -#define G1_REG_INTERRUPT_DEC_IRQ BIT(8) -#define G1_REG_INTERRUPT_DEC_IRQ_DIS BIT(4) -#define G1_REG_INTERRUPT_DEC_E BIT(0) +/* Interrupt bits. Some are present in: + * - all core versions (">= g1") + * - g1, missing in g2, but added back starting with vc8000d ("not in g2") + * - vc8000d and later (">= vc8000d") + */ +#define G1_REG_INTERRUPT_DEC_PIC_INF BIT(24) /* not in g2 */ +#define G1_REG_INTERRUPT_DEC_TILE_INT BIT(23) /* >= vc8000d */ +#define G1_REG_INTERRUPT_DEC_LINE_CNT_INT BIT(22) /* >= vc8000d */ +#define G1_REG_INTERRUPT_DEC_EXT_TIMEOUT_INT BIT(21) /* >= vc8000d */ +#define G1_REG_INTERRUPT_DEC_NO_SLICE_INT BIT(20) /* >= vc8000d */ +#define G1_REG_INTERRUPT_DEC_LAST_SLICE_INT BIT(19) /* >= vc8000d */ +#define G1_REG_INTERRUPT_DEC_TIMEOUT BIT(18) /* >= g1 */ +#define G1_REG_INTERRUPT_DEC_SLICE_INT BIT(17) /* not in g2 */ +#define G1_REG_INTERRUPT_DEC_ERROR_INT BIT(16) /* >= g1 */ +#define G1_REG_INTERRUPT_DEC_ASO_INT BIT(15) /* not in g2 */ +#define G1_REG_INTERRUPT_DEC_BUFFER_INT BIT(14) /* >= g1 */ +#define G1_REG_INTERRUPT_DEC_BUS_INT BIT(13) /* >= g1 */ +#define G1_REG_INTERRUPT_DEC_RDY_INT BIT(12) /* >= g1 */ +#define G1_REG_INTERRUPT_DEC_ABORT_INT BIT(11) /* >= g2 */ +#define G1_REG_INTERRUPT_DEC_IRQ BIT(8) /* >= g1 */ +#define G1_REG_INTERRUPT_DEC_TILE_INT_E BIT(7) /* >= vc8000d */ +#define G1_REG_INTERRUPT_DEC_SELF_RESET_DIS BIT(6) /* >= vc8000d */ +#define G1_REG_INTERRUPT_DEC_ABORT_E BIT(5) /* >= vc8000d */ +#define G1_REG_INTERRUPT_DEC_IRQ_DIS BIT(4) /* >= g1 */ +#define G1_REG_INTERRUPT_DEC_TIMEOUT_SOURCE BIT(3) /* >= vc8000d */ +#define G1_REG_INTERRUPT_DEC_BUS_INT_DIS BIT(2) /* >= vc8000d */ +#define G1_REG_INTERRUPT_DEC_STRM_CORRUPTED BIT(1) /* >= vc8000d */ +#define G1_REG_INTERRUPT_DEC_E BIT(0) /* >= g1 */ #define G1_REG_CONFIG 0x008 #define G1_REG_CONFIG_DEC_AXI_RD_ID(x) (((x) & 0xff) << 24) #define G1_REG_CONFIG_DEC_TIMEOUT_E BIT(23) -- 2.28.0
WARNING: multiple messages have this Message-ID (diff)
From: Adrian Ratiu <adrian.ratiu@collabora.com> To: Ezequiel Garcia <ezequiel@collabora.com>, Philipp Zabel <p.zabel@pengutronix.de> Cc: Fruehberger Peter <Peter.Fruehberger@de.bosch.com>, Mauro Carvalho Chehab <mchehab@kernel.org>, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, Mark Brown <broonie@kernel.org>, kuhanh.murugasen.krishnan@intel.com, Daniel Vetter <daniel@ffwll.ch>, kernel@collabora.com, linux-media@vger.kernel.org Subject: [PATCH 01/18] media: hantro: document all int reg bits up to vc8000 Date: Mon, 12 Oct 2020 23:59:40 +0300 [thread overview] Message-ID: <20201012205957.889185-2-adrian.ratiu@collabora.com> (raw) In-Reply-To: <20201012205957.889185-1-adrian.ratiu@collabora.com> These do not all strictly belong to the g1 core and even the majority of previously documented bits were not used (yet) by the driver irq handlers, but it's still very useful to have an overview of all IRQs, especially since starting with core versions vc8000 and later the irq bits previously used by G1 and G2 have been merged at the same address. Signed-off-by: Adrian Ratiu <adrian.ratiu@collabora.com> --- drivers/staging/media/hantro/hantro_g1_regs.h | 39 +++++++++++++------ 1 file changed, 28 insertions(+), 11 deletions(-) diff --git a/drivers/staging/media/hantro/hantro_g1_regs.h b/drivers/staging/media/hantro/hantro_g1_regs.h index c1756e3d5391..80ff297f6f68 100644 --- a/drivers/staging/media/hantro/hantro_g1_regs.h +++ b/drivers/staging/media/hantro/hantro_g1_regs.h @@ -13,17 +13,34 @@ /* Decoder registers. */ #define G1_REG_INTERRUPT 0x004 -#define G1_REG_INTERRUPT_DEC_PIC_INF BIT(24) -#define G1_REG_INTERRUPT_DEC_TIMEOUT BIT(18) -#define G1_REG_INTERRUPT_DEC_SLICE_INT BIT(17) -#define G1_REG_INTERRUPT_DEC_ERROR_INT BIT(16) -#define G1_REG_INTERRUPT_DEC_ASO_INT BIT(15) -#define G1_REG_INTERRUPT_DEC_BUFFER_INT BIT(14) -#define G1_REG_INTERRUPT_DEC_BUS_INT BIT(13) -#define G1_REG_INTERRUPT_DEC_RDY_INT BIT(12) -#define G1_REG_INTERRUPT_DEC_IRQ BIT(8) -#define G1_REG_INTERRUPT_DEC_IRQ_DIS BIT(4) -#define G1_REG_INTERRUPT_DEC_E BIT(0) +/* Interrupt bits. Some are present in: + * - all core versions (">= g1") + * - g1, missing in g2, but added back starting with vc8000d ("not in g2") + * - vc8000d and later (">= vc8000d") + */ +#define G1_REG_INTERRUPT_DEC_PIC_INF BIT(24) /* not in g2 */ +#define G1_REG_INTERRUPT_DEC_TILE_INT BIT(23) /* >= vc8000d */ +#define G1_REG_INTERRUPT_DEC_LINE_CNT_INT BIT(22) /* >= vc8000d */ +#define G1_REG_INTERRUPT_DEC_EXT_TIMEOUT_INT BIT(21) /* >= vc8000d */ +#define G1_REG_INTERRUPT_DEC_NO_SLICE_INT BIT(20) /* >= vc8000d */ +#define G1_REG_INTERRUPT_DEC_LAST_SLICE_INT BIT(19) /* >= vc8000d */ +#define G1_REG_INTERRUPT_DEC_TIMEOUT BIT(18) /* >= g1 */ +#define G1_REG_INTERRUPT_DEC_SLICE_INT BIT(17) /* not in g2 */ +#define G1_REG_INTERRUPT_DEC_ERROR_INT BIT(16) /* >= g1 */ +#define G1_REG_INTERRUPT_DEC_ASO_INT BIT(15) /* not in g2 */ +#define G1_REG_INTERRUPT_DEC_BUFFER_INT BIT(14) /* >= g1 */ +#define G1_REG_INTERRUPT_DEC_BUS_INT BIT(13) /* >= g1 */ +#define G1_REG_INTERRUPT_DEC_RDY_INT BIT(12) /* >= g1 */ +#define G1_REG_INTERRUPT_DEC_ABORT_INT BIT(11) /* >= g2 */ +#define G1_REG_INTERRUPT_DEC_IRQ BIT(8) /* >= g1 */ +#define G1_REG_INTERRUPT_DEC_TILE_INT_E BIT(7) /* >= vc8000d */ +#define G1_REG_INTERRUPT_DEC_SELF_RESET_DIS BIT(6) /* >= vc8000d */ +#define G1_REG_INTERRUPT_DEC_ABORT_E BIT(5) /* >= vc8000d */ +#define G1_REG_INTERRUPT_DEC_IRQ_DIS BIT(4) /* >= g1 */ +#define G1_REG_INTERRUPT_DEC_TIMEOUT_SOURCE BIT(3) /* >= vc8000d */ +#define G1_REG_INTERRUPT_DEC_BUS_INT_DIS BIT(2) /* >= vc8000d */ +#define G1_REG_INTERRUPT_DEC_STRM_CORRUPTED BIT(1) /* >= vc8000d */ +#define G1_REG_INTERRUPT_DEC_E BIT(0) /* >= g1 */ #define G1_REG_CONFIG 0x008 #define G1_REG_CONFIG_DEC_AXI_RD_ID(x) (((x) & 0xff) << 24) #define G1_REG_CONFIG_DEC_TIMEOUT_E BIT(23) -- 2.28.0 _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip
next prev parent reply other threads:[~2020-10-12 20:58 UTC|newest] Thread overview: 68+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-10-12 20:59 [PATCH 00/18] Add Hantro regmap and VC8000 h264 decode support Adrian Ratiu 2020-10-12 20:59 ` Adrian Ratiu 2020-10-12 20:59 ` Adrian Ratiu [this message] 2020-10-12 20:59 ` [PATCH 01/18] media: hantro: document all int reg bits up to vc8000 Adrian Ratiu 2020-10-12 20:59 ` [PATCH 02/18] media: hantro: make consistent use of decimal register notation Adrian Ratiu 2020-10-12 20:59 ` Adrian Ratiu 2020-10-12 20:59 ` [PATCH 03/18] media: hantro: make G1_REG_SOFT_RESET Rockchip specific Adrian Ratiu 2020-10-12 20:59 ` Adrian Ratiu 2020-10-12 20:59 ` [PATCH 04/18] media: hantro: add reset controller support Adrian Ratiu 2020-10-12 20:59 ` Adrian Ratiu 2020-10-13 8:11 ` Philipp Zabel 2020-10-13 8:11 ` Philipp Zabel 2020-10-12 20:59 ` [PATCH 05/18] media: hantro: prepare clocks before variant inits are run Adrian Ratiu 2020-10-12 20:59 ` Adrian Ratiu 2020-10-12 20:59 ` [PATCH 06/18] media: hantro: imx8mq: simplify ctrlblk reset logic Adrian Ratiu 2020-10-12 20:59 ` Adrian Ratiu 2020-10-12 20:59 ` [PATCH 07/18] regmap: mmio: add config option to allow relaxed MMIO accesses Adrian Ratiu 2020-10-12 20:59 ` Adrian Ratiu 2020-10-13 10:26 ` Mark Brown 2020-10-13 10:26 ` Mark Brown 2020-10-14 11:51 ` Adrian Ratiu 2020-10-14 11:51 ` Adrian Ratiu 2020-10-14 12:12 ` Mark Brown 2020-10-14 12:12 ` Mark Brown 2020-10-14 13:00 ` Adrian Ratiu 2020-10-14 13:00 ` Adrian Ratiu 2020-10-12 20:59 ` [PATCH 08/18] media: hantro: add initial MMIO regmap infrastructure Adrian Ratiu 2020-10-12 20:59 ` Adrian Ratiu 2020-10-12 20:59 ` [PATCH 09/18] media: hantro: default regmap to relaxed MMIO Adrian Ratiu 2020-10-12 20:59 ` Adrian Ratiu 2020-10-12 20:59 ` [PATCH 10/18] media: hantro: convert G1 h264 decoder to regmap fields Adrian Ratiu 2020-10-12 20:59 ` Adrian Ratiu 2020-10-12 20:59 ` [PATCH 11/18] media: hantro: convert G1 postproc to regmap Adrian Ratiu 2020-10-12 20:59 ` Adrian Ratiu 2020-10-12 20:59 ` [PATCH 12/18] media: hantro: add VC8000D h264 decoding Adrian Ratiu 2020-10-12 20:59 ` Adrian Ratiu 2020-10-12 20:59 ` [PATCH 13/18] media: hantro: add VC8000D postproc support Adrian Ratiu 2020-10-12 20:59 ` Adrian Ratiu 2020-10-12 20:59 ` [PATCH 14/18] media: hantro: make PP enablement logic a bit smarter Adrian Ratiu 2020-10-12 20:59 ` Adrian Ratiu 2020-10-12 20:59 ` [PATCH 15/18] media: hantro: add user-selectable, platform-selectable H264 High10 Adrian Ratiu 2020-10-12 20:59 ` Adrian Ratiu 2020-10-12 20:59 ` [PATCH 16/18] media: hantro: rename h264_dec as it's not G1 specific anymore Adrian Ratiu 2020-10-12 20:59 ` Adrian Ratiu 2020-10-12 20:59 ` [PATCH 17/18] media: hantro: add dump registers debug option before decode start Adrian Ratiu 2020-10-12 20:59 ` Adrian Ratiu 2020-10-12 20:59 ` [PATCH 18/18] media: hantro: document encoder reg fields Adrian Ratiu 2020-10-12 20:59 ` Adrian Ratiu 2020-10-12 23:39 ` [PATCH 00/18] Add Hantro regmap and VC8000 h264 decode support Jonas Karlman 2020-10-12 23:39 ` Jonas Karlman 2020-10-13 6:48 ` Adrian Ratiu 2020-10-13 6:48 ` Adrian Ratiu 2020-10-29 12:38 ` Ezequiel Garcia 2020-10-29 12:38 ` Ezequiel Garcia 2020-10-29 16:21 ` Jonas Karlman 2020-10-29 16:21 ` Jonas Karlman 2020-11-03 15:27 ` Ezequiel Garcia 2020-11-03 15:27 ` Ezequiel Garcia 2020-10-29 13:07 ` Ezequiel Garcia 2020-10-29 13:07 ` Ezequiel Garcia 2020-10-29 14:15 ` Robin Murphy 2020-10-29 14:15 ` Robin Murphy 2020-10-29 14:48 ` Mark Brown 2020-10-29 14:48 ` Mark Brown 2020-10-29 16:27 ` Ezequiel Garcia 2020-10-29 16:27 ` Ezequiel Garcia 2020-10-29 17:59 ` Mark Brown 2020-10-29 17:59 ` Mark Brown
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