From: Miles Chen <miles.chen@mediatek.com>
To: Catalin Marinas <catalin.marinas@arm.com>,
Russell King <linux@armlinux.org.uk>,
Minchan Kim <minchan@kernel.org>
Cc: <linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>,
<linux-mediatek@lists.infradead.org>, <wsd_upstream@mediatek.com>,
Will Deacon <will.deacon@arm.com>,
Steve Capper <steve.capper@linaro.org>,
Simon Horman <horms@verge.net.au>,
Suren Baghdasaryan <surenb@google.com>,
Miles Chen <miles.chen@mediatek.com>
Subject: [PATCH v2 2/4] arm: mm: reordering memory type table
Date: Fri, 23 Oct 2020 17:14:35 +0800 [thread overview]
Message-ID: <20201023091437.8225-3-miles.chen@mediatek.com> (raw)
In-Reply-To: <20201023091437.8225-1-miles.chen@mediatek.com>
From: Minchan Kim <minchan@kernel.org>
To use bit 5 in page table as L_PTE_SPECIAL, we need a room for that.
It seems we don't need 4 bits for the memory type with ARMv6+.
If it's true, let's reorder bits to make bit 5 free.
We will use the bit for L_PTE_SPECIAL in next patch.
A note from Catalin in [1]:
"
> Anyway, on ARMv7 or ARMv6+LPAE, the non-shared device gets mapped to
> shared device in hardware. Looking through the arm32 code, it seems that
> MT_DEVICE_NONSHARED is used by arch/arm/mach-shmobile/setup-r8a7779.c
> and IIUC that's a v7 platform (R-Car H1, Cortex-A9). I think the above
> should be defined to L_PTE_MT_DEV_SHARED, unless I miss any place where
> DEV_NONSHARED is relevant on ARMv6 (adding Simon to confirm on shmbile).
"
[1] https://lore.kernel.org/patchwork/patch/986574/
Cc: Russell King <linux@armlinux.org.uk>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Steve Capper <steve.capper@linaro.org>
Cc: Simon Horman <horms@verge.net.au>
Cc: Minchan Kim <minchan@kernel.org>
Cc: Suren Baghdasaryan <surenb@google.com>
Signed-off-by: Minchan Kim <minchan@kernel.org>
Signed-off-by: Miles Chen <miles.chen@mediatek.com>
---
arch/arm/include/asm/pgtable-2level.h | 21 +++++++++++++++++----
arch/arm/mm/proc-macros.S | 4 ++--
2 files changed, 19 insertions(+), 6 deletions(-)
diff --git a/arch/arm/include/asm/pgtable-2level.h b/arch/arm/include/asm/pgtable-2level.h
index 27a8635abea0..cdcd55cca37d 100644
--- a/arch/arm/include/asm/pgtable-2level.h
+++ b/arch/arm/include/asm/pgtable-2level.h
@@ -161,14 +161,27 @@
#define L_PTE_MT_BUFFERABLE (_AT(pteval_t, 0x01) << 2) /* 0001 */
#define L_PTE_MT_WRITETHROUGH (_AT(pteval_t, 0x02) << 2) /* 0010 */
#define L_PTE_MT_WRITEBACK (_AT(pteval_t, 0x03) << 2) /* 0011 */
+#define L_PTE_MT_DEV_SHARED (_AT(pteval_t, 0x04) << 2) /* 0100 */
+#define L_PTE_MT_VECTORS (_AT(pteval_t, 0x05) << 2) /* 0101 */
#define L_PTE_MT_MINICACHE (_AT(pteval_t, 0x06) << 2) /* 0110 (sa1100, xscale) */
#define L_PTE_MT_WRITEALLOC (_AT(pteval_t, 0x07) << 2) /* 0111 */
-#define L_PTE_MT_DEV_SHARED (_AT(pteval_t, 0x04) << 2) /* 0100 */
-#define L_PTE_MT_DEV_NONSHARED (_AT(pteval_t, 0x0c) << 2) /* 1100 */
+#if defined(CONFIG_CPU_V7) || defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K)
+/*
+ * On ARMv7 or ARMv7+LPAE, the non-shared and shared device types get
+ * mapped to the same TEX remapping index. On classic ARMv7, the
+ * shareability is controlled by the PRRR[17:16] field, indexed by
+ * L_PTE_SHARED. On ARMv7+LPAE the device mapping is always shareable.
+ */
+#define L_PTE_MT_DEV_NONSHARED L_PTE_MT_DEV_SHARED
+#define L_PTE_MT_DEV_WC L_PTE_MT_BUFFERABLE
+#define L_PTE_MT_DEV_CACHED L_PTE_MT_WRITEBACK
+#define L_PTE_MT_MASK (_AT(pteval_t, 0x07) << 2)
+#else
#define L_PTE_MT_DEV_WC (_AT(pteval_t, 0x09) << 2) /* 1001 */
#define L_PTE_MT_DEV_CACHED (_AT(pteval_t, 0x0b) << 2) /* 1011 */
-#define L_PTE_MT_VECTORS (_AT(pteval_t, 0x0f) << 2) /* 1111 */
-#define L_PTE_MT_MASK (_AT(pteval_t, 0x0f) << 2)
+#define L_PTE_MT_DEV_NONSHARED (_AT(pteval_t, 0x0c) << 2) /* 1100 */
+#define L_PTE_MT_MASK (_AT(pteval_t, 0x0f) << 2)
+#endif
#ifndef __ASSEMBLY__
diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S
index e2c743aa2eb2..dde1d6374250 100644
--- a/arch/arm/mm/proc-macros.S
+++ b/arch/arm/mm/proc-macros.S
@@ -137,7 +137,7 @@
.long PTE_CACHEABLE @ L_PTE_MT_WRITETHROUGH
.long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEBACK
.long PTE_BUFFERABLE @ L_PTE_MT_DEV_SHARED
- .long 0x00 @ unused
+ .long PTE_CACHEABLE | PTE_BUFFERABLE | PTE_EXT_APX @ L_PTE_MT_VECTORS
.long 0x00 @ L_PTE_MT_MINICACHE (not present)
.long PTE_EXT_TEX(1) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEALLOC
.long 0x00 @ unused
@@ -147,7 +147,7 @@
.long PTE_EXT_TEX(2) @ L_PTE_MT_DEV_NONSHARED
.long 0x00 @ unused
.long 0x00 @ unused
- .long PTE_CACHEABLE | PTE_BUFFERABLE | PTE_EXT_APX @ L_PTE_MT_VECTORS
+ .long 0x00 @ unused
.endm
.macro armv6_set_pte_ext pfx
--
2.18.0
WARNING: multiple messages have this Message-ID (diff)
From: Miles Chen <miles.chen@mediatek.com>
To: Catalin Marinas <catalin.marinas@arm.com>,
Russell King <linux@armlinux.org.uk>,
Minchan Kim <minchan@kernel.org>
Cc: Steve Capper <steve.capper@linaro.org>,
wsd_upstream@mediatek.com, Will Deacon <will.deacon@arm.com>,
linux-kernel@vger.kernel.org,
Miles Chen <miles.chen@mediatek.com>,
Simon Horman <horms@verge.net.au>,
linux-mediatek@lists.infradead.org,
Suren Baghdasaryan <surenb@google.com>,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 2/4] arm: mm: reordering memory type table
Date: Fri, 23 Oct 2020 17:14:35 +0800 [thread overview]
Message-ID: <20201023091437.8225-3-miles.chen@mediatek.com> (raw)
In-Reply-To: <20201023091437.8225-1-miles.chen@mediatek.com>
From: Minchan Kim <minchan@kernel.org>
To use bit 5 in page table as L_PTE_SPECIAL, we need a room for that.
It seems we don't need 4 bits for the memory type with ARMv6+.
If it's true, let's reorder bits to make bit 5 free.
We will use the bit for L_PTE_SPECIAL in next patch.
A note from Catalin in [1]:
"
> Anyway, on ARMv7 or ARMv6+LPAE, the non-shared device gets mapped to
> shared device in hardware. Looking through the arm32 code, it seems that
> MT_DEVICE_NONSHARED is used by arch/arm/mach-shmobile/setup-r8a7779.c
> and IIUC that's a v7 platform (R-Car H1, Cortex-A9). I think the above
> should be defined to L_PTE_MT_DEV_SHARED, unless I miss any place where
> DEV_NONSHARED is relevant on ARMv6 (adding Simon to confirm on shmbile).
"
[1] https://lore.kernel.org/patchwork/patch/986574/
Cc: Russell King <linux@armlinux.org.uk>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Steve Capper <steve.capper@linaro.org>
Cc: Simon Horman <horms@verge.net.au>
Cc: Minchan Kim <minchan@kernel.org>
Cc: Suren Baghdasaryan <surenb@google.com>
Signed-off-by: Minchan Kim <minchan@kernel.org>
Signed-off-by: Miles Chen <miles.chen@mediatek.com>
---
arch/arm/include/asm/pgtable-2level.h | 21 +++++++++++++++++----
arch/arm/mm/proc-macros.S | 4 ++--
2 files changed, 19 insertions(+), 6 deletions(-)
diff --git a/arch/arm/include/asm/pgtable-2level.h b/arch/arm/include/asm/pgtable-2level.h
index 27a8635abea0..cdcd55cca37d 100644
--- a/arch/arm/include/asm/pgtable-2level.h
+++ b/arch/arm/include/asm/pgtable-2level.h
@@ -161,14 +161,27 @@
#define L_PTE_MT_BUFFERABLE (_AT(pteval_t, 0x01) << 2) /* 0001 */
#define L_PTE_MT_WRITETHROUGH (_AT(pteval_t, 0x02) << 2) /* 0010 */
#define L_PTE_MT_WRITEBACK (_AT(pteval_t, 0x03) << 2) /* 0011 */
+#define L_PTE_MT_DEV_SHARED (_AT(pteval_t, 0x04) << 2) /* 0100 */
+#define L_PTE_MT_VECTORS (_AT(pteval_t, 0x05) << 2) /* 0101 */
#define L_PTE_MT_MINICACHE (_AT(pteval_t, 0x06) << 2) /* 0110 (sa1100, xscale) */
#define L_PTE_MT_WRITEALLOC (_AT(pteval_t, 0x07) << 2) /* 0111 */
-#define L_PTE_MT_DEV_SHARED (_AT(pteval_t, 0x04) << 2) /* 0100 */
-#define L_PTE_MT_DEV_NONSHARED (_AT(pteval_t, 0x0c) << 2) /* 1100 */
+#if defined(CONFIG_CPU_V7) || defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K)
+/*
+ * On ARMv7 or ARMv7+LPAE, the non-shared and shared device types get
+ * mapped to the same TEX remapping index. On classic ARMv7, the
+ * shareability is controlled by the PRRR[17:16] field, indexed by
+ * L_PTE_SHARED. On ARMv7+LPAE the device mapping is always shareable.
+ */
+#define L_PTE_MT_DEV_NONSHARED L_PTE_MT_DEV_SHARED
+#define L_PTE_MT_DEV_WC L_PTE_MT_BUFFERABLE
+#define L_PTE_MT_DEV_CACHED L_PTE_MT_WRITEBACK
+#define L_PTE_MT_MASK (_AT(pteval_t, 0x07) << 2)
+#else
#define L_PTE_MT_DEV_WC (_AT(pteval_t, 0x09) << 2) /* 1001 */
#define L_PTE_MT_DEV_CACHED (_AT(pteval_t, 0x0b) << 2) /* 1011 */
-#define L_PTE_MT_VECTORS (_AT(pteval_t, 0x0f) << 2) /* 1111 */
-#define L_PTE_MT_MASK (_AT(pteval_t, 0x0f) << 2)
+#define L_PTE_MT_DEV_NONSHARED (_AT(pteval_t, 0x0c) << 2) /* 1100 */
+#define L_PTE_MT_MASK (_AT(pteval_t, 0x0f) << 2)
+#endif
#ifndef __ASSEMBLY__
diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S
index e2c743aa2eb2..dde1d6374250 100644
--- a/arch/arm/mm/proc-macros.S
+++ b/arch/arm/mm/proc-macros.S
@@ -137,7 +137,7 @@
.long PTE_CACHEABLE @ L_PTE_MT_WRITETHROUGH
.long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEBACK
.long PTE_BUFFERABLE @ L_PTE_MT_DEV_SHARED
- .long 0x00 @ unused
+ .long PTE_CACHEABLE | PTE_BUFFERABLE | PTE_EXT_APX @ L_PTE_MT_VECTORS
.long 0x00 @ L_PTE_MT_MINICACHE (not present)
.long PTE_EXT_TEX(1) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEALLOC
.long 0x00 @ unused
@@ -147,7 +147,7 @@
.long PTE_EXT_TEX(2) @ L_PTE_MT_DEV_NONSHARED
.long 0x00 @ unused
.long 0x00 @ unused
- .long PTE_CACHEABLE | PTE_BUFFERABLE | PTE_EXT_APX @ L_PTE_MT_VECTORS
+ .long 0x00 @ unused
.endm
.macro armv6_set_pte_ext pfx
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
WARNING: multiple messages have this Message-ID (diff)
From: Miles Chen <miles.chen@mediatek.com>
To: Catalin Marinas <catalin.marinas@arm.com>,
Russell King <linux@armlinux.org.uk>,
Minchan Kim <minchan@kernel.org>
Cc: Steve Capper <steve.capper@linaro.org>,
wsd_upstream@mediatek.com, Will Deacon <will.deacon@arm.com>,
linux-kernel@vger.kernel.org,
Miles Chen <miles.chen@mediatek.com>,
Simon Horman <horms@verge.net.au>,
linux-mediatek@lists.infradead.org,
Suren Baghdasaryan <surenb@google.com>,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 2/4] arm: mm: reordering memory type table
Date: Fri, 23 Oct 2020 17:14:35 +0800 [thread overview]
Message-ID: <20201023091437.8225-3-miles.chen@mediatek.com> (raw)
In-Reply-To: <20201023091437.8225-1-miles.chen@mediatek.com>
From: Minchan Kim <minchan@kernel.org>
To use bit 5 in page table as L_PTE_SPECIAL, we need a room for that.
It seems we don't need 4 bits for the memory type with ARMv6+.
If it's true, let's reorder bits to make bit 5 free.
We will use the bit for L_PTE_SPECIAL in next patch.
A note from Catalin in [1]:
"
> Anyway, on ARMv7 or ARMv6+LPAE, the non-shared device gets mapped to
> shared device in hardware. Looking through the arm32 code, it seems that
> MT_DEVICE_NONSHARED is used by arch/arm/mach-shmobile/setup-r8a7779.c
> and IIUC that's a v7 platform (R-Car H1, Cortex-A9). I think the above
> should be defined to L_PTE_MT_DEV_SHARED, unless I miss any place where
> DEV_NONSHARED is relevant on ARMv6 (adding Simon to confirm on shmbile).
"
[1] https://lore.kernel.org/patchwork/patch/986574/
Cc: Russell King <linux@armlinux.org.uk>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Steve Capper <steve.capper@linaro.org>
Cc: Simon Horman <horms@verge.net.au>
Cc: Minchan Kim <minchan@kernel.org>
Cc: Suren Baghdasaryan <surenb@google.com>
Signed-off-by: Minchan Kim <minchan@kernel.org>
Signed-off-by: Miles Chen <miles.chen@mediatek.com>
---
arch/arm/include/asm/pgtable-2level.h | 21 +++++++++++++++++----
arch/arm/mm/proc-macros.S | 4 ++--
2 files changed, 19 insertions(+), 6 deletions(-)
diff --git a/arch/arm/include/asm/pgtable-2level.h b/arch/arm/include/asm/pgtable-2level.h
index 27a8635abea0..cdcd55cca37d 100644
--- a/arch/arm/include/asm/pgtable-2level.h
+++ b/arch/arm/include/asm/pgtable-2level.h
@@ -161,14 +161,27 @@
#define L_PTE_MT_BUFFERABLE (_AT(pteval_t, 0x01) << 2) /* 0001 */
#define L_PTE_MT_WRITETHROUGH (_AT(pteval_t, 0x02) << 2) /* 0010 */
#define L_PTE_MT_WRITEBACK (_AT(pteval_t, 0x03) << 2) /* 0011 */
+#define L_PTE_MT_DEV_SHARED (_AT(pteval_t, 0x04) << 2) /* 0100 */
+#define L_PTE_MT_VECTORS (_AT(pteval_t, 0x05) << 2) /* 0101 */
#define L_PTE_MT_MINICACHE (_AT(pteval_t, 0x06) << 2) /* 0110 (sa1100, xscale) */
#define L_PTE_MT_WRITEALLOC (_AT(pteval_t, 0x07) << 2) /* 0111 */
-#define L_PTE_MT_DEV_SHARED (_AT(pteval_t, 0x04) << 2) /* 0100 */
-#define L_PTE_MT_DEV_NONSHARED (_AT(pteval_t, 0x0c) << 2) /* 1100 */
+#if defined(CONFIG_CPU_V7) || defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K)
+/*
+ * On ARMv7 or ARMv7+LPAE, the non-shared and shared device types get
+ * mapped to the same TEX remapping index. On classic ARMv7, the
+ * shareability is controlled by the PRRR[17:16] field, indexed by
+ * L_PTE_SHARED. On ARMv7+LPAE the device mapping is always shareable.
+ */
+#define L_PTE_MT_DEV_NONSHARED L_PTE_MT_DEV_SHARED
+#define L_PTE_MT_DEV_WC L_PTE_MT_BUFFERABLE
+#define L_PTE_MT_DEV_CACHED L_PTE_MT_WRITEBACK
+#define L_PTE_MT_MASK (_AT(pteval_t, 0x07) << 2)
+#else
#define L_PTE_MT_DEV_WC (_AT(pteval_t, 0x09) << 2) /* 1001 */
#define L_PTE_MT_DEV_CACHED (_AT(pteval_t, 0x0b) << 2) /* 1011 */
-#define L_PTE_MT_VECTORS (_AT(pteval_t, 0x0f) << 2) /* 1111 */
-#define L_PTE_MT_MASK (_AT(pteval_t, 0x0f) << 2)
+#define L_PTE_MT_DEV_NONSHARED (_AT(pteval_t, 0x0c) << 2) /* 1100 */
+#define L_PTE_MT_MASK (_AT(pteval_t, 0x0f) << 2)
+#endif
#ifndef __ASSEMBLY__
diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S
index e2c743aa2eb2..dde1d6374250 100644
--- a/arch/arm/mm/proc-macros.S
+++ b/arch/arm/mm/proc-macros.S
@@ -137,7 +137,7 @@
.long PTE_CACHEABLE @ L_PTE_MT_WRITETHROUGH
.long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEBACK
.long PTE_BUFFERABLE @ L_PTE_MT_DEV_SHARED
- .long 0x00 @ unused
+ .long PTE_CACHEABLE | PTE_BUFFERABLE | PTE_EXT_APX @ L_PTE_MT_VECTORS
.long 0x00 @ L_PTE_MT_MINICACHE (not present)
.long PTE_EXT_TEX(1) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEALLOC
.long 0x00 @ unused
@@ -147,7 +147,7 @@
.long PTE_EXT_TEX(2) @ L_PTE_MT_DEV_NONSHARED
.long 0x00 @ unused
.long 0x00 @ unused
- .long PTE_CACHEABLE | PTE_BUFFERABLE | PTE_EXT_APX @ L_PTE_MT_VECTORS
+ .long 0x00 @ unused
.endm
.macro armv6_set_pte_ext pfx
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-10-23 9:15 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-23 9:14 [PATCH v2 0/4] arm: support get_user_pages_fast Miles Chen
2020-10-23 9:14 ` Miles Chen
2020-10-23 9:14 ` Miles Chen
2020-10-23 9:14 ` [PATCH v2 1/4] arm: mm: use strict p[gum]d types Miles Chen
2020-10-23 9:14 ` Miles Chen
2020-10-23 9:14 ` Miles Chen
2020-10-23 9:14 ` Miles Chen [this message]
2020-10-23 9:14 ` [PATCH v2 2/4] arm: mm: reordering memory type table Miles Chen
2020-10-23 9:14 ` Miles Chen
2020-10-23 10:16 ` Russell King - ARM Linux admin
2020-10-23 10:16 ` Russell King - ARM Linux admin
2020-10-23 10:16 ` Russell King - ARM Linux admin
2020-10-27 8:03 ` Miles Chen
2020-10-27 8:03 ` Miles Chen
2020-10-27 8:03 ` Miles Chen
2020-10-23 9:14 ` [PATCH v2 3/4] arm: mm: introduce L_PTE_SPECIAL Miles Chen
2020-10-23 9:14 ` Miles Chen
2020-10-23 9:14 ` Miles Chen
2020-10-23 10:08 ` Russell King - ARM Linux admin
2020-10-23 10:08 ` Russell King - ARM Linux admin
2020-10-23 10:08 ` Russell King - ARM Linux admin
2020-10-27 7:45 ` Miles Chen
2020-10-27 7:45 ` Miles Chen
2020-10-27 7:45 ` Miles Chen
2020-10-27 9:11 ` Russell King - ARM Linux admin
2020-10-27 9:11 ` Russell King - ARM Linux admin
2020-10-27 9:11 ` Russell King - ARM Linux admin
2020-11-01 12:48 ` Miles Chen
2020-11-01 12:48 ` Miles Chen
2020-11-01 12:48 ` Miles Chen
2020-10-23 9:14 ` [PATCH v2 4/4] arm: replace vector mem type with read-only type Miles Chen
2020-10-23 9:14 ` Miles Chen
2020-10-23 9:14 ` Miles Chen
2020-10-23 10:12 ` Russell King - ARM Linux admin
2020-10-23 10:12 ` Russell King - ARM Linux admin
2020-10-23 10:12 ` Russell King - ARM Linux admin
2020-10-27 7:41 ` Miles Chen
2020-10-27 7:41 ` Miles Chen
2020-10-27 7:41 ` Miles Chen
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