From: Dmitry Osipenko <digetx@gmail.com> To: Thierry Reding <thierry.reding@gmail.com>, Jonathan Hunter <jonathanh@nvidia.com>, Georgi Djakov <georgi.djakov@linaro.org>, Rob Herring <robh+dt@kernel.org>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Peter De Schrijver <pdeschrijver@nvidia.com>, MyungJoo Ham <myungjoo.ham@samsung.com>, Kyungmin Park <kyungmin.park@samsung.com>, Chanwoo Choi <cw00.choi@samsung.com>, Mikko Perttunen <cyndis@kapsi.fi>, Viresh Kumar <vireshk@kernel.org>, Peter Geis <pgwipeout@gmail.com>, Nicolas Chauvet <kwizart@gmail.com>, Krzysztof Kozlowski <krzk@kernel.org> Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v7 16/47] dt-bindings: host1x: Document new interconnect properties Date: Wed, 4 Nov 2020 19:48:52 +0300 [thread overview] Message-ID: <20201104164923.21238-17-digetx@gmail.com> (raw) In-Reply-To: <20201104164923.21238-1-digetx@gmail.com> Most of Host1x devices have at least one memory client. These clients are directly connected to the memory controller. The new interconnect properties represent the memory client's connection to the memory controller. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> --- .../display/tegra/nvidia,tegra20-host1x.txt | 68 +++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt index ac63ae4a3861..34d993338453 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt @@ -20,6 +20,10 @@ Required properties: - reset-names: Must include the following entries: - host1x +Each host1x client module having to perform DMA through the Memory Controller +should have the interconnect endpoints set to the Memory Client and External +Memory respectively. + The host1x top-level node defines a number of children, each representing one of the following host1x client modules: @@ -36,6 +40,12 @@ of the following host1x client modules: - reset-names: Must include the following entries: - mpe + Optional properties: + - interconnects: Must contain entry for the MPE memory clients. + - interconnect-names: Must include name of the interconnect path for each + interconnect entry. Consult TRM documentation for information about + available memory clients, see MEMORY CONTROLLER section. + - vi: video input Required properties: @@ -113,6 +123,12 @@ of the following host1x client modules: Required properties: - remote-endpoint: phandle to vi port 'endpoint' node. + Optional properties: + - interconnects: Must contain entry for the VI memory clients. + - interconnect-names: Must include name of the interconnect path for each + interconnect entry. Consult TRM documentation for information about + available memory clients, see MEMORY CONTROLLER section. + - epp: encoder pre-processor Required properties: @@ -126,6 +142,12 @@ of the following host1x client modules: - reset-names: Must include the following entries: - epp + Optional properties: + - interconnects: Must contain entry for the EPP memory clients. + - interconnect-names: Must include name of the interconnect path for each + interconnect entry. Consult TRM documentation for information about + available memory clients, see MEMORY CONTROLLER section. + - isp: image signal processor Required properties: @@ -139,6 +161,12 @@ of the following host1x client modules: - reset-names: Must include the following entries: - isp + Optional properties: + - interconnects: Must contain entry for the ISP memory clients. + - interconnect-names: Must include name of the interconnect path for each + interconnect entry. Consult TRM documentation for information about + available memory clients, see MEMORY CONTROLLER section. + - gr2d: 2D graphics engine Required properties: @@ -152,6 +180,12 @@ of the following host1x client modules: - reset-names: Must include the following entries: - 2d + Optional properties: + - interconnects: Must contain entry for the GR2D memory clients. + - interconnect-names: Must include name of the interconnect path for each + interconnect entry. Consult TRM documentation for information about + available memory clients, see MEMORY CONTROLLER section. + - gr3d: 3D graphics engine Required properties: @@ -170,6 +204,12 @@ of the following host1x client modules: - 3d - 3d2 (Only required on SoCs with two 3D clocks) + Optional properties: + - interconnects: Must contain entry for the GR3D memory clients. + - interconnect-names: Must include name of the interconnect path for each + interconnect entry. Consult TRM documentation for information about + available memory clients, see MEMORY CONTROLLER section. + - dc: display controller Required properties: @@ -197,6 +237,10 @@ of the following host1x client modules: - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection - nvidia,edid: supplies a binary EDID blob - nvidia,panel: phandle of a display panel + - interconnects: Must contain entry for the DC memory clients. + - interconnect-names: Must include name of the interconnect path for each + interconnect entry. Consult TRM documentation for information about + available memory clients, see MEMORY CONTROLLER section. - hdmi: High Definition Multimedia Interface @@ -345,6 +389,12 @@ of the following host1x client modules: - reset-names: Must include the following entries: - vic + Optional properties: + - interconnects: Must contain entry for the VIC memory clients. + - interconnect-names: Must include name of the interconnect path for each + interconnect entry. Consult TRM documentation for information about + available memory clients, see MEMORY CONTROLLER section. + Example: / { @@ -498,6 +548,15 @@ Example: resets = <&tegra_car 27>; reset-names = "dc"; + interconnects = <&mc TEGRA20_MC_DISPLAY0A &emc>, + <&mc TEGRA20_MC_DISPLAY0B &emc>, + <&mc TEGRA20_MC_DISPLAY0C &emc>, + <&mc TEGRA20_MC_DISPLAYHC &emc>; + interconnect-names = "wina", + "winb", + "winc", + "cursor"; + rgb { status = "disabled"; }; @@ -513,6 +572,15 @@ Example: resets = <&tegra_car 26>; reset-names = "dc"; + interconnects = <&mc TEGRA20_MC_DISPLAY0AB &emc>, + <&mc TEGRA20_MC_DISPLAY0BB &emc>, + <&mc TEGRA20_MC_DISPLAY0CB &emc>, + <&mc TEGRA20_MC_DISPLAYHCB &emc>; + interconnect-names = "wina", + "winb", + "winc", + "cursor"; + rgb { status = "disabled"; }; -- 2.27.0
WARNING: multiple messages have this Message-ID (diff)
From: Dmitry Osipenko <digetx@gmail.com> To: Thierry Reding <thierry.reding@gmail.com>, Jonathan Hunter <jonathanh@nvidia.com>, Georgi Djakov <georgi.djakov@linaro.org>, Rob Herring <robh+dt@kernel.org>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Peter De Schrijver <pdeschrijver@nvidia.com>, MyungJoo Ham <myungjoo.ham@samsung.com>, Kyungmin Park <kyungmin.park@samsung.com>, Chanwoo Choi <cw00.choi@samsung.com>, Mikko Perttunen <cyndis@kapsi.fi>, Viresh Kumar <vireshk@kernel.org>, Peter Geis <pgwipeout@gmail.com>, Nicolas Chauvet <kwizart@gmail.com>, Krzysztof Kozlowski <krzk@kernel.org> Cc: linux-tegra@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org Subject: [PATCH v7 16/47] dt-bindings: host1x: Document new interconnect properties Date: Wed, 4 Nov 2020 19:48:52 +0300 [thread overview] Message-ID: <20201104164923.21238-17-digetx@gmail.com> (raw) In-Reply-To: <20201104164923.21238-1-digetx@gmail.com> Most of Host1x devices have at least one memory client. These clients are directly connected to the memory controller. The new interconnect properties represent the memory client's connection to the memory controller. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> --- .../display/tegra/nvidia,tegra20-host1x.txt | 68 +++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt index ac63ae4a3861..34d993338453 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt @@ -20,6 +20,10 @@ Required properties: - reset-names: Must include the following entries: - host1x +Each host1x client module having to perform DMA through the Memory Controller +should have the interconnect endpoints set to the Memory Client and External +Memory respectively. + The host1x top-level node defines a number of children, each representing one of the following host1x client modules: @@ -36,6 +40,12 @@ of the following host1x client modules: - reset-names: Must include the following entries: - mpe + Optional properties: + - interconnects: Must contain entry for the MPE memory clients. + - interconnect-names: Must include name of the interconnect path for each + interconnect entry. Consult TRM documentation for information about + available memory clients, see MEMORY CONTROLLER section. + - vi: video input Required properties: @@ -113,6 +123,12 @@ of the following host1x client modules: Required properties: - remote-endpoint: phandle to vi port 'endpoint' node. + Optional properties: + - interconnects: Must contain entry for the VI memory clients. + - interconnect-names: Must include name of the interconnect path for each + interconnect entry. Consult TRM documentation for information about + available memory clients, see MEMORY CONTROLLER section. + - epp: encoder pre-processor Required properties: @@ -126,6 +142,12 @@ of the following host1x client modules: - reset-names: Must include the following entries: - epp + Optional properties: + - interconnects: Must contain entry for the EPP memory clients. + - interconnect-names: Must include name of the interconnect path for each + interconnect entry. Consult TRM documentation for information about + available memory clients, see MEMORY CONTROLLER section. + - isp: image signal processor Required properties: @@ -139,6 +161,12 @@ of the following host1x client modules: - reset-names: Must include the following entries: - isp + Optional properties: + - interconnects: Must contain entry for the ISP memory clients. + - interconnect-names: Must include name of the interconnect path for each + interconnect entry. Consult TRM documentation for information about + available memory clients, see MEMORY CONTROLLER section. + - gr2d: 2D graphics engine Required properties: @@ -152,6 +180,12 @@ of the following host1x client modules: - reset-names: Must include the following entries: - 2d + Optional properties: + - interconnects: Must contain entry for the GR2D memory clients. + - interconnect-names: Must include name of the interconnect path for each + interconnect entry. Consult TRM documentation for information about + available memory clients, see MEMORY CONTROLLER section. + - gr3d: 3D graphics engine Required properties: @@ -170,6 +204,12 @@ of the following host1x client modules: - 3d - 3d2 (Only required on SoCs with two 3D clocks) + Optional properties: + - interconnects: Must contain entry for the GR3D memory clients. + - interconnect-names: Must include name of the interconnect path for each + interconnect entry. Consult TRM documentation for information about + available memory clients, see MEMORY CONTROLLER section. + - dc: display controller Required properties: @@ -197,6 +237,10 @@ of the following host1x client modules: - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection - nvidia,edid: supplies a binary EDID blob - nvidia,panel: phandle of a display panel + - interconnects: Must contain entry for the DC memory clients. + - interconnect-names: Must include name of the interconnect path for each + interconnect entry. Consult TRM documentation for information about + available memory clients, see MEMORY CONTROLLER section. - hdmi: High Definition Multimedia Interface @@ -345,6 +389,12 @@ of the following host1x client modules: - reset-names: Must include the following entries: - vic + Optional properties: + - interconnects: Must contain entry for the VIC memory clients. + - interconnect-names: Must include name of the interconnect path for each + interconnect entry. Consult TRM documentation for information about + available memory clients, see MEMORY CONTROLLER section. + Example: / { @@ -498,6 +548,15 @@ Example: resets = <&tegra_car 27>; reset-names = "dc"; + interconnects = <&mc TEGRA20_MC_DISPLAY0A &emc>, + <&mc TEGRA20_MC_DISPLAY0B &emc>, + <&mc TEGRA20_MC_DISPLAY0C &emc>, + <&mc TEGRA20_MC_DISPLAYHC &emc>; + interconnect-names = "wina", + "winb", + "winc", + "cursor"; + rgb { status = "disabled"; }; @@ -513,6 +572,15 @@ Example: resets = <&tegra_car 26>; reset-names = "dc"; + interconnects = <&mc TEGRA20_MC_DISPLAY0AB &emc>, + <&mc TEGRA20_MC_DISPLAY0BB &emc>, + <&mc TEGRA20_MC_DISPLAY0CB &emc>, + <&mc TEGRA20_MC_DISPLAYHCB &emc>; + interconnect-names = "wina", + "winb", + "winc", + "cursor"; + rgb { status = "disabled"; }; -- 2.27.0 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
next prev parent reply other threads:[~2020-11-04 16:53 UTC|newest] Thread overview: 188+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-11-04 16:48 [PATCH v7 00/47] Introduce memory interconnect for NVIDIA Tegra SoCs Dmitry Osipenko 2020-11-04 16:48 ` Dmitry Osipenko 2020-11-04 16:48 ` [PATCH v7 01/47] clk: tegra: Export Tegra20 EMC kernel symbols Dmitry Osipenko 2020-11-04 16:48 ` Dmitry Osipenko 2020-11-06 18:23 ` Krzysztof Kozlowski 2020-11-06 18:23 ` Krzysztof Kozlowski 2020-11-04 16:48 ` [PATCH v7 02/47] soc/tegra: fuse: Export tegra_read_ram_code() Dmitry Osipenko 2020-11-04 16:48 ` Dmitry Osipenko 2020-11-06 18:24 ` Krzysztof Kozlowski 2020-11-06 18:24 ` Krzysztof Kozlowski 2020-11-04 16:48 ` [PATCH v7 03/47] soc/tegra: fuse: Add stub for tegra_sku_info Dmitry Osipenko 2020-11-04 16:48 ` Dmitry Osipenko 2020-11-06 18:25 ` Krzysztof Kozlowski 2020-11-06 18:25 ` Krzysztof Kozlowski 2020-11-04 16:48 ` [PATCH v7 04/47] dt-bindings: memory: tegra20: emc: Correct registers range in example Dmitry Osipenko 2020-11-04 16:48 ` Dmitry Osipenko 2020-11-06 18:28 ` Krzysztof Kozlowski 2020-11-06 18:28 ` Krzysztof Kozlowski 2020-11-04 16:48 ` [PATCH v7 05/47] dt-bindings: memory: tegra20: emc: Document nvidia,memory-controller property Dmitry Osipenko 2020-11-04 16:48 ` [PATCH v7 05/47] dt-bindings: memory: tegra20: emc: Document nvidia, memory-controller property Dmitry Osipenko 2020-11-06 18:29 ` [PATCH v7 05/47] dt-bindings: memory: tegra20: emc: Document nvidia,memory-controller property Krzysztof Kozlowski 2020-11-06 18:29 ` Krzysztof Kozlowski 2020-11-04 16:48 ` [PATCH v7 06/47] dt-bindings: memory: tegra20: mc: Document new interconnect property Dmitry Osipenko 2020-11-04 16:48 ` Dmitry Osipenko 2020-11-06 18:30 ` Krzysztof Kozlowski 2020-11-06 18:30 ` Krzysztof Kozlowski 2020-11-04 16:48 ` [PATCH v7 07/47] dt-bindings: memory: tegra20: emc: " Dmitry Osipenko 2020-11-04 16:48 ` Dmitry Osipenko 2020-11-06 18:30 ` Krzysztof Kozlowski 2020-11-06 18:30 ` Krzysztof Kozlowski 2020-11-04 16:48 ` [PATCH v7 08/47] dt-bindings: memory: tegra20: emc: Document OPP table and voltage regulator Dmitry Osipenko 2020-11-04 16:48 ` Dmitry Osipenko 2020-11-05 19:48 ` Rob Herring 2020-11-05 19:48 ` Rob Herring 2020-11-06 18:31 ` Krzysztof Kozlowski 2020-11-06 18:31 ` Krzysztof Kozlowski 2020-11-04 16:48 ` [PATCH v7 09/47] dt-bindings: memory: tegra30: mc: Document new interconnect property Dmitry Osipenko 2020-11-04 16:48 ` Dmitry Osipenko 2020-11-06 18:31 ` Krzysztof Kozlowski 2020-11-06 18:31 ` Krzysztof Kozlowski 2020-11-04 16:48 ` [PATCH v7 10/47] dt-bindings: memory: tegra30: emc: " Dmitry Osipenko 2020-11-04 16:48 ` Dmitry Osipenko 2020-11-06 18:31 ` Krzysztof Kozlowski 2020-11-06 18:31 ` Krzysztof Kozlowski 2020-11-04 16:48 ` [PATCH v7 11/47] dt-bindings: memory: tegra30: emc: Document OPP table and voltage regulator Dmitry Osipenko 2020-11-04 16:48 ` Dmitry Osipenko 2020-11-06 18:32 ` Krzysztof Kozlowski 2020-11-06 18:32 ` Krzysztof Kozlowski 2020-11-04 16:48 ` [PATCH v7 12/47] dt-bindings: memory: tegra124: mc: Document new interconnect property Dmitry Osipenko 2020-11-04 16:48 ` Dmitry Osipenko 2020-11-05 19:49 ` Rob Herring 2020-11-05 19:49 ` Rob Herring 2020-11-06 18:33 ` Krzysztof Kozlowski 2020-11-06 18:33 ` Krzysztof Kozlowski 2020-11-04 16:48 ` [PATCH v7 13/47] dt-bindings: memory: tegra124: emc: " Dmitry Osipenko 2020-11-04 16:48 ` Dmitry Osipenko 2020-11-06 18:34 ` Krzysztof Kozlowski 2020-11-06 18:34 ` Krzysztof Kozlowski 2020-11-04 16:48 ` [PATCH v7 14/47] dt-bindings: memory: tegra124: emc: Document OPP table and voltage regulator Dmitry Osipenko 2020-11-04 16:48 ` Dmitry Osipenko 2020-11-06 18:36 ` Krzysztof Kozlowski 2020-11-06 18:36 ` Krzysztof Kozlowski 2020-11-04 16:48 ` [PATCH v7 15/47] dt-bindings: tegra30-actmon: Document OPP and interconnect properties Dmitry Osipenko 2020-11-04 16:48 ` Dmitry Osipenko 2020-11-06 18:34 ` Krzysztof Kozlowski 2020-11-06 18:34 ` Krzysztof Kozlowski 2020-11-04 16:48 ` Dmitry Osipenko [this message] 2020-11-04 16:48 ` [PATCH v7 16/47] dt-bindings: host1x: Document new " Dmitry Osipenko 2020-11-06 18:36 ` Krzysztof Kozlowski 2020-11-06 18:36 ` Krzysztof Kozlowski 2020-11-04 16:48 ` [PATCH v7 17/47] dt-bindings: memory: tegra20: Add memory client IDs Dmitry Osipenko 2020-11-04 16:48 ` Dmitry Osipenko 2020-11-06 18:38 ` Krzysztof Kozlowski 2020-11-06 18:38 ` Krzysztof Kozlowski 2020-11-26 17:26 ` Thierry Reding 2020-11-26 17:26 ` Thierry Reding 2020-11-26 17:39 ` Krzysztof Kozlowski 2020-11-26 17:39 ` Krzysztof Kozlowski 2020-11-26 17:45 ` Krzysztof Kozlowski 2020-11-26 17:45 ` Krzysztof Kozlowski 2020-11-26 17:55 ` Krzysztof Kozlowski 2020-11-26 17:55 ` Krzysztof Kozlowski 2020-11-26 17:59 ` Thierry Reding 2020-11-26 17:59 ` Thierry Reding 2020-11-26 18:02 ` Thierry Reding 2020-11-26 18:02 ` Thierry Reding 2020-11-26 18:06 ` Krzysztof Kozlowski 2020-11-26 18:06 ` Krzysztof Kozlowski 2020-11-04 16:48 ` [PATCH v7 18/47] dt-bindings: memory: tegra30: " Dmitry Osipenko 2020-11-04 16:48 ` Dmitry Osipenko 2020-11-06 18:38 ` Krzysztof Kozlowski 2020-11-06 18:38 ` Krzysztof Kozlowski 2020-11-26 17:55 ` Krzysztof Kozlowski 2020-11-26 17:55 ` Krzysztof Kozlowski 2020-11-04 16:48 ` [PATCH v7 19/47] dt-bindings: memory: tegra124: " Dmitry Osipenko 2020-11-04 16:48 ` Dmitry Osipenko 2020-11-06 18:39 ` Krzysztof Kozlowski 2020-11-06 18:39 ` Krzysztof Kozlowski 2020-11-26 17:55 ` Krzysztof Kozlowski 2020-11-26 17:55 ` Krzysztof Kozlowski 2020-11-04 16:48 ` [PATCH v7 20/47] ARM: tegra: Correct EMC registers size in Tegra20 device-tree Dmitry Osipenko 2020-11-04 16:48 ` Dmitry Osipenko 2020-11-04 16:48 ` [PATCH v7 21/47] ARM: tegra: Add interconnect properties to " Dmitry Osipenko 2020-11-04 16:48 ` Dmitry Osipenko 2020-11-04 16:48 ` [PATCH v7 22/47] ARM: tegra: Add interconnect properties to Tegra30 device-tree Dmitry Osipenko 2020-11-04 16:48 ` Dmitry Osipenko 2020-11-04 16:48 ` [PATCH v7 23/47] ARM: tegra: Add interconnect properties to Tegra124 device-tree Dmitry Osipenko 2020-11-04 16:48 ` Dmitry Osipenko 2020-11-04 16:49 ` [PATCH v7 24/47] ARM: tegra: Add nvidia,memory-controller phandle to Tegra20 EMC device-tree Dmitry Osipenko 2020-11-04 16:49 ` [PATCH v7 24/47] ARM: tegra: Add nvidia, memory-controller " Dmitry Osipenko 2020-11-04 16:49 ` [PATCH v7 25/47] ARM: tegra: Add DVFS properties to Tegra20 EMC device-tree node Dmitry Osipenko 2020-11-04 16:49 ` Dmitry Osipenko 2020-11-04 16:49 ` [PATCH v7 26/47] ARM: tegra: Add DVFS properties to Tegra30 EMC and ACTMON device-tree nodes Dmitry Osipenko 2020-11-04 16:49 ` Dmitry Osipenko 2020-11-04 16:49 ` [PATCH v7 27/47] ARM: tegra: Add DVFS properties to Tegra124 " Dmitry Osipenko 2020-11-04 16:49 ` Dmitry Osipenko 2020-11-04 16:49 ` [PATCH v7 28/47] memory: tegra: Add and use devm_tegra_memory_controller_get() Dmitry Osipenko 2020-11-04 16:49 ` Dmitry Osipenko 2020-11-06 19:02 ` Krzysztof Kozlowski 2020-11-06 19:02 ` Krzysztof Kozlowski 2020-11-04 16:49 ` [PATCH v7 29/47] memory: tegra: Use devm_platform_ioremap_resource() Dmitry Osipenko 2020-11-04 16:49 ` Dmitry Osipenko 2020-11-06 19:03 ` Krzysztof Kozlowski 2020-11-06 19:03 ` Krzysztof Kozlowski 2020-11-04 16:49 ` [PATCH v7 30/47] memory: tegra: Remove superfluous error messages around platform_get_irq() Dmitry Osipenko 2020-11-04 16:49 ` Dmitry Osipenko 2020-11-06 19:04 ` Krzysztof Kozlowski 2020-11-06 19:04 ` Krzysztof Kozlowski 2020-11-04 16:49 ` [PATCH v7 31/47] memory: tegra: Add missing latency allowness entry for Page Table Cache Dmitry Osipenko 2020-11-04 16:49 ` Dmitry Osipenko 2020-11-06 19:05 ` Krzysztof Kozlowski 2020-11-06 19:05 ` Krzysztof Kozlowski 2020-11-04 16:49 ` [PATCH v7 32/47] memory: tegra-mc: Add interconnect framework Dmitry Osipenko 2020-11-04 16:49 ` Dmitry Osipenko 2020-11-06 19:07 ` Krzysztof Kozlowski 2020-11-06 19:07 ` Krzysztof Kozlowski 2020-11-04 16:49 ` [PATCH v7 33/47] memory: tegra20-emc: Make driver modular Dmitry Osipenko 2020-11-04 16:49 ` Dmitry Osipenko 2020-11-06 19:07 ` Krzysztof Kozlowski 2020-11-06 19:07 ` Krzysztof Kozlowski 2020-11-04 16:49 ` [PATCH v7 34/47] memory: tegra20-emc: Continue probing if timings are missing in device-tree Dmitry Osipenko 2020-11-04 16:49 ` Dmitry Osipenko 2020-11-06 19:08 ` Krzysztof Kozlowski 2020-11-06 19:08 ` Krzysztof Kozlowski 2020-11-04 16:49 ` [PATCH v7 35/47] memory: tegra20: Support interconnect framework Dmitry Osipenko 2020-11-04 16:49 ` Dmitry Osipenko 2020-11-06 19:10 ` Krzysztof Kozlowski 2020-11-06 19:10 ` Krzysztof Kozlowski 2020-11-04 16:49 ` [PATCH v7 36/47] memory: tegra20-emc: Add devfreq support Dmitry Osipenko 2020-11-04 16:49 ` Dmitry Osipenko 2020-11-05 2:30 ` Chanwoo Choi 2020-11-05 2:30 ` Chanwoo Choi 2020-11-05 13:50 ` Dmitry Osipenko 2020-11-05 13:50 ` Dmitry Osipenko 2020-11-06 19:13 ` Krzysztof Kozlowski 2020-11-06 19:13 ` Krzysztof Kozlowski 2020-11-06 21:53 ` Dmitry Osipenko 2020-11-04 16:49 ` [PATCH v7 37/47] memory: tegra30: Add FIFO sizes to memory clients Dmitry Osipenko 2020-11-04 16:49 ` Dmitry Osipenko 2020-11-04 16:49 ` [PATCH v7 38/47] memory: tegra30-emc: Make driver modular Dmitry Osipenko 2020-11-04 16:49 ` Dmitry Osipenko 2020-11-04 16:49 ` [PATCH v7 39/47] memory: tegra30-emc: Continue probing if timings are missing in device-tree Dmitry Osipenko 2020-11-04 16:49 ` Dmitry Osipenko 2020-11-04 16:49 ` [PATCH v7 40/47] memory: tegra30: Support interconnect framework Dmitry Osipenko 2020-11-04 16:49 ` Dmitry Osipenko 2020-11-04 16:49 ` [PATCH v7 41/47] memory: tegra124-emc: Make driver modular Dmitry Osipenko 2020-11-04 16:49 ` Dmitry Osipenko 2020-11-04 16:49 ` [PATCH v7 42/47] memory: tegra124: Support interconnect framework Dmitry Osipenko 2020-11-04 16:49 ` Dmitry Osipenko 2020-11-04 16:49 ` [PATCH v7 43/47] drm/tegra: dc: Support memory bandwidth management Dmitry Osipenko 2020-11-04 16:49 ` Dmitry Osipenko 2020-11-09 4:02 ` kernel test robot 2020-11-04 16:49 ` [PATCH v7 44/47] drm/tegra: dc: Extend debug stats with total number of events Dmitry Osipenko 2020-11-04 16:49 ` Dmitry Osipenko 2020-11-04 16:49 ` [PATCH v7 45/47] PM / devfreq: tegra30: Support interconnect and OPPs from device-tree Dmitry Osipenko 2020-11-04 16:49 ` Dmitry Osipenko 2020-11-05 2:22 ` Chanwoo Choi 2020-11-05 2:22 ` Chanwoo Choi 2020-11-04 16:49 ` [PATCH v7 46/47] PM / devfreq: tegra30: Separate configurations per-SoC generation Dmitry Osipenko 2020-11-04 16:49 ` Dmitry Osipenko 2020-11-05 2:23 ` Chanwoo Choi 2020-11-05 2:23 ` Chanwoo Choi 2020-11-04 16:49 ` [PATCH v7 47/47] PM / devfreq: tegra20: Deprecate in a favor of emc-stat based driver Dmitry Osipenko 2020-11-04 16:49 ` Dmitry Osipenko 2020-11-05 2:25 ` Chanwoo Choi 2020-11-05 2:25 ` Chanwoo Choi 2020-11-05 13:50 ` Dmitry Osipenko 2020-11-05 13:50 ` Dmitry Osipenko
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